Systems and methods for sharing a serial communication port between a plurality of communication channels

Patent metadata

Field	Value
Publication number	US-9602433-B2
Application number	US-201313841355-A
Country	US
Kind code	B2
Filing date	Mar 15, 2013
Priority date	Jul 26, 2012
Publication date	Mar 21, 2017
Grant date	Mar 21, 2017

Abstract

An apparatus for sharing a serial communication port between a plurality of communication channels is described. The apparatus comprises a transceiver that manages communications over the serial communication port. The apparatus also includes a multiplexer coupled to the transceiver, wherein the multiplexer multiplexes the plurality of communication channels. The apparatus also includes identification information circuitry coupled to the multiplexer, wherein the identification information circuitry adds identification information to data from the plurality of communication channels that enables the plurality of communication channels to share the serial communication port. The serial communications port and the multiplexer permit communication between integrated circuits that meet at least one latency metric for the plurality of communication channels when the plurality of communication channels are active.

First claim

What is claimed is:

1. An apparatus for sharing a serial communication port between a plurality of communication channels, comprising:
a transceiver that manages communications over the serial communication port;
a multiplexer coupled to the transceiver, wherein the multiplexer multiplexes the plurality of communication channels; and
identification information circuitry coupled to the multiplexer, wherein the identification information circuitry adds identification information to data from the plurality of communication channels that enables the plurality of communication channels to share the serial communication port;
wherein the serial communication port and the multiplexer permit bi-directional communication between a modem in the apparatus and an analog chip in the apparatus coupled together by a high-speed clock line serial link that meet at least one latency metric for the plurality of communication channels when each of the plurality of communication channels is active.

2. The apparatus of claim 1 , wherein the apparatus is positioned on an integrated circuit.

3. The apparatus of claim 1 , wherein each of the plurality of communication channels is a wire line channel.

4. The apparatus of claim 1 , wherein the plurality of communication channels corresponds to a plurality of serial communication standards, and wherein the plurality of serial communication standards comprises a universal serial bus communication standard and a peripheral component interconnect express communication standard.

5. The apparatus of claim 4 , wherein the identification information identifies which serial communication standard of the plurality of serial communication standards corresponds to each communication channel of the plurality of communication channels.

6. The apparatus of claim 1 , wherein the plurality of communication channels corresponds to a plurality of instances of a communication standard.

7. The apparatus of claim 1 , wherein the plurality of communication channels corresponds to physical layer standards.

8. The apparatus of claim 1 , wherein the at least one latency metric includes a metric for determining whether an integrated circuit transmits data, wherein the metric corresponds to a communication channel property.

9. The apparatus of claim 8 , wherein the integrated circuit transmits data when the communication channel property is greater than the metric.

10. The apparatus of claim 1 , wherein the at least one latency metric includes a bandwidth metric.

11. The apparatus of claim 1 , wherein the at least one latency metric includes a data transfer rate metric.

12. The apparatus of claim 1 , wherein the at least one latency metric does not include a buffering metric.

13. The apparatus of claim 1 , wherein the integrated circuits are in a chip-to-chip configuration.

14. A method for sharing a serial communication port between a plurality of communication channels by an apparatus, comprising:
managing communications over the serial communication port;
multiplexing the plurality of communication channels;
adding identification information to data from the plurality of communication channels that enables the plurality of communication channels to share the serial communication port; and
permitting bi-directional communication between a modem in the apparatus and an analog chip in the apparatus coupled together by a high-speed clock line serial link that meet at least one latency metric for the plurality of communication channels when each of the plurality of communication channels is active.

15. The method of claim 14 , wherein the apparatus is positioned on an integrated circuit.

16. The method of claim 14 , wherein each of the plurality of communication channels is a wire line channel.

17. The method of claim 14 , wherein the plurality of communication channels corresponds to a plurality of communication standards.

18. The method of claim 14 , wherein the plurality of communication channels corresponds to a plurality of instances of a communication standard.

19. The method of claim 14 , wherein the plurality of communication channels corresponds to physical layer standards.

20. The method of claim 14 , further comprising identifying a communication standard.

21. The method of claim 14 , wherein the at least one latency metric includes a metric for determining whether an integrated circuit transmits data, wherein the metric corresponds to a communication channel property.

22. The method of claim 21 , further comprising transmitting data when the communication channel property is greater than the metric.

23. The method of claim 14 , wherein the at least one latency metric includes a bandwidth metric.

24. The method of claim 14 , wherein the at least one latency metric includes a data transfer rate metric.

25. The method of claim 14 , wherein the at least one latency metric does not include a buffering metric.

26. The method of claim 14 , wherein the integrated circuits are in a chip-to-chip configuration.

27. A computer-program product for sharing a serial communication port between a plurality of communication channels, comprising a non-transitory tangible computer-readable medium having instructions thereon, the instructions comprising:
code for causing an apparatus to manage communications over the serial communication port;
code for causing the apparatus to multiplex the plurality of communication channels;
code for causing the apparatus to add identification information to data from the plurality of communication channels that enables the plurality of communication channels to share the serial communication port; and
code for causing the apparatus to permit bi-directional communication between a modem in the apparatus and an analog chip in the apparatus coupled together by a high-speed clock line serial link that meet at least one latency metric for the plurality of communication channels when each of the plurality of communication channels is active.

28. The computer-program product of claim 27 , wherein the plurality of communication channels corresponds to a plurality of communication standards.

29. The computer-program product of claim 27 , wherein the plurality of communication channels corresponds to a plurality of instances of a communication standard.

30. The computer-program product of claim 27 , wherein the plurality of communication channels corresponds to physical layer standards.

31. The computer-program product of claim 27 , wherein the instructions further comprise code for causing the apparatus to identify a communication standard.

32. The computer-program product of claim 27 , wherein the at least one latency metric includes a metric for determining whether an integrated circuit transmits data, wherein the metric corresponds to a communication channel property.

33. The computer-program product of claim 32 , wherein the instructions further comprise code for causing the apparatus to transmit data when the communication channel property is greater than the metric.

34. The computer-program product of claim 27 , wherein the at least one latency metric does not include a buffering metric.

35. An apparatus for sharing a serial communication port between a plurality of communication channels, co

Assignees

• Qualcomm Inc

Inventors

• Huang Xuhao
• Srivastava Ankit
• Quan Xiaohong
• Bazarjani Seyfollah S

Classifications

• H04L12/4035

  in which slots of a TDMA packet structure are assigned based on a contention resolution carried out at a master unit (TDM/TDMA multiplex systems per se H04J3/1694; hybrid switching systems H04L12/64) · CPC title

• H04L12/40006 Primary

  Architecture of a communication node (current supply arrangements H04L12/10; intermediate storage or scheduling H04L49/90) · CPC title

• H04L25/0272

  Arrangements for coupling to multiple lines, e.g. for differential transmission · CPC title

• H04L49/25 Primary

  Routing or path finding in a switch fabric · CPC title