Single event latch-up protection for fault current residing inside the normal operating current range

Patent metadata

Field	Value
Publication number	US-11522361-B2
Application number	US-202117395658-A
Country	US
Kind code	B2
Filing date	Aug 6, 2021
Priority date	Feb 19, 2019
Publication date	Dec 6, 2022
Grant date	Dec 6, 2022

Abstract

Embodiments of a single event latch-up (SEL) protection circuit are provided, including: a first circuitry block coupled to a source of an input voltage a load, and digitally controlling a first switch; the first switch generates a load and senses an instantaneous load current iLoad. A second circuitry block is configured to generate an average iLoad and generate single event latch-up triggers (i.e., SEL fault detection) as a function of at least a comparison of the inst_iLoad and average iLoad; wherein this first circuitry block contains the analog based SET filtering needed to reduce false SEL triggers. A supervisor module generates on/off commands for the first switch, responsive to receiving the SEL detection in excess of a pre-programmed delay to provide the final SET filtering to prevent false SEL triggers. The first circuitry block removes the load voltage at N 1 upon receiving an off command from the supervisor module.

First claim

What is claimed is:

1. A single event latch-up (SEL) detection circuit, comprising:
a first circuitry block coupled to a source of an input voltage V 1 , the first circuitry block configured to (i) receive the input voltage V 1 , a digital enable signal L_en, and an on command, and to control a gate voltage (Vgate) as a function of the input voltage V 1 , the digital enable signal L_en, and the on command, and (ii) sense an instantaneous load current, inst_iLoad at a node N 2 ;
a first switch configured to receive Vgate, and to control a load voltage at a node N 1 , responsive to the Vgate;
a load ohmically coupled to N 1 ;
a second circuitry block coupled to the first circuitry block at N 2 and configured to (i) receive V 1 and inst_iLoad, (ii) generate an average load current (iLoad), and (iii) generate a single event latch-up trigger (SEL_T) at a node N 3 , the SEL_T being a function of at least a comparison of the inst_iLoad and the average load current (iLoad); and
a supervisor module coupled between the second circuitry block at N 3 and the first circuitry block, the supervisor module configured to receive the SEL_T, and generate an off command when the SEL_T remains asserted a pre-programmed delay after the receipt of the SEL_T;
wherein the first circuitry block is further configured to remove the load voltage at N 1 upon receiving an off command, and
wherein the supervisor module is further configured to:
upon receiving the SEL_T, determine that a step load current of the source of the input voltage V 1 falls within a predicted range while exceeding a maximum step load current; and
prevent generation of the off command responsive thereto.

2. The SEL protection circuit of claim 1 , wherein the switch is implemented with at least a field effect transistor (FET) having its gate controlled by a combination of the L_en signal and the on/off commands, its drain directly connected to N 2 , and its source ohmically coupled to N 1 .

3. The SEL protection circuit of claim 2 , wherein the first circuitry block comprises an analog circuitry configured to receive the L_en and to actively pull the load voltage at N 1 to substantially zero volts when L_en is low, and to cease actively pulling the load voltage at N 1 low responsive to L_en going high.

4. The SEL protection circuit of claim 3 , wherein the second circuitry block comprises:
a first and a second operational amplifier, each configured to compare the average load current (iLoad) to the inst_iLoad; and wherein output signals from the first and second operational amplifier are attenuated with a filter to generate the single event latch-up trigger (SEL_T) therefrom.

5. The SEL protection circuit of claim 4 , wherein the supervisor module is configured to:
provide a second digital preprogramed delay; and
generate the off command responsive to the elapse of the second digital pre-programmed delay after receipt of the SEL_T.

6. The SEL protection circuit of claim 5 , wherein, responsive to power asserted at V 1 , the first circuitry block is configured to:
hold the load voltage at N 1 low when L_en is low; and,
generate the load voltage at N 1 responsive to receiving the on command when the L_en signal is asserted and V 1 is asserted.

7. The SEL protection circuit of claim 6 , further comprising
active discharge circuitry coupled between N 1 and ground, the active discharge circuitry including a second switch configured to actively drain current from N 1 when the first switch is off.

8. The SEL protection circuit of claim 1 , wherein the source of the input voltage V 1 has a fault current that is greater than a step load current, and wherein the SEL control circuitry is further adapted to remove the load voltage at N 1 for a range of iLoad between the step load current and the fault current.

9. A single event latch-up (SEL) detection circuit, comprising:
a first circuitry block coupled to a source of an input voltage V 1 , the first circuitry block configured to (i) receive the input voltage V 1 , a digital enable signal L_en, and an on command, and to control a gate voltage (Vgate) as a function of the input voltage V 1 , the digital enable signal L_en, and the on command, and (ii) sense an instantaneous load current, inst_iLoad at a node N 2 ;
a first switch configured to receive Vgate, and to control a load voltage at a node N 1 , responsive to the Vgate;
a load ohmically coupled to N 1 ;
a second circuitry block coupled to the first circuitry block at N 2 and configured to (i) receive V 1 and inst_iLoad, (ii) generate an average load current (iLoad), and (iii) generate a single event latch-up trigger (SEL_T) at a node N 3 , the SEL_T being a function of at least a comparison of the inst_iLoad and the average load current (iLoad); and
a supervisor module coupled between the second circuitry block at N 3 and the first circuitry block, the supervisor module configured to receive the SEL_T, and generate an off command when the SEL_T remains asserted a pre-programmed delay after the receipt of the SEL_T,
wherein the first circuitry block is further configured to remove the load voltage at N 1 upon receiving an off command, and
wherein the supervisor module is further configured to take no action in response to (i) detecting SEL_T and (ii) detecting that a step load current of the source of the input voltage V 1 exceeds a maximum step load current.

Assignees

• Honeywell Int Inc

Inventors

• Schwerman Paul W
• Brown Jr George M
• Marshall Richard L

Classifications

• H02H1/0007

  concerning the detecting means (in general G01R or other subclasses of G01; reed switches H01H71/2445) · CPC title

• H02H5/005 Primary

  responsive to ionising radiation; Nuclear-radiation circumvention circuits (radiation detectors G01T; nuclear-explosion detection G21J5/00) · CPC title

• H02H3/0935

  the timing being determined by numerical means · CPC title

• H02H9/025 Primary

  Current limitation using field effect transistors · CPC title