Devices and methods for accessing resistive change elements in resistive change element arrays
US-2019115054-A1 · Apr 18, 2019 · US
Metal insulator transition field programmable routing block
US11522130B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-11522130-B2 |
| Application number | US-201816022685-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jun 28, 2018 |
| Priority date | Jun 28, 2018 |
| Publication date | Dec 6, 2022 |
| Grant date | Dec 6, 2022 |
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- Title
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- Abstract
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- Assignees and inventors
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- Key dates
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- First independent claim
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- CPC / IPC classifications
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- Citations and related patents
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Abstract
Official abstract text for this publication.
A routing structure is disclosed. A first wiring line coupled to a programming access device and a routing block driver and receiver enabling device and a second wiring line coupled to a programming access device and a routing block driver and receiver enabling device. An insulator-metal-transistor device that includes a top electrode, a middle electrode and a bottom electrode, coupled at the intersection of the first wiring line and the second wiring line.
First claim
Opening claim text (preview).
What is claimed is: 1. A routing structure, comprising: a first wiring line coupled to a first programming access device and a routing block driver and receiver enabling device, wherein the first wiring line is formed in a first metallic layer; a second wiring line coupled to a second programming access device and a routing block driver and receiver enabling device, wherein the second wiring line is formed in a second metallic layer that is vertically displaced from the first metallic layer; and an insulator-metal-transition (IMT) device coupled at the intersection of the first wiring line and the second wiring line, the IMT device coupled directly to the first wiring line and to the second wiring line. 2. The routing structure of claim 1 , wherein the IMT device is configured to conduct electrical signals in a RLOW state. 3. The routing structure of claim 1 , wherein the IMT device is a part of a RRAM free crosspoint. 4. The routing structure of claim 1 , wherein the IMT device is configured to assume a state determined by a programming voltage. 5. The routing structure of claim 1 , wherein the IMT device is configured to selectively couple inputs and outputs. 6. The routing structure of claim 1 , wherein the IMT device is configured to hold a configuration state until it is reconfigured. 7. The routing structure of claim 1 , wherein the IMT device is a part of an FPGA backend. 8. A routing structure, comprising: a plurality of horizontal wiring lines coupled to first programming access devices and routing block driver and receiver enabling devices, wherein each of the horizonal wiring lines is formed in a first metallic layer; a plurality of vertical wiring lines coupled to second programming access devices and routing block driver and receiver enabling devices, wherein each of the vertical wiring lines is formed in a second metallic layer that is vertically displaced from the first metallic layer; and a plurality of insulator-metal-transition devices coupled at the intersection of the plurality of horizontal wiring lines and the plurality of vertical wiring lines, each of the insulator-metal- transistor devices coupled directly to a corresponding one of the plurality of horizontal wiring lines and to a corresponding one of the plurality of vertical wiring lines. 9. The routing structure of claim 8 , wherein the IMT devices are configured to conduct electrical signals in a RLOW state. 10. The routing structure of claim 9 , wherein the IMT devices are a part of a RRAM free crosspoint. 11. The routing structure of claim 9 , wherein the IMT devices are configured to assume a state determined by a programming voltage. 12. The routing structure of claim 9 , wherein the IMT devices are configured to selectively couple inputs and outputs. 13. The routing structure of claim 9 , wherein the IMT devices are configured to hold a configuration state until it is reconfigured. 14. The routing structure of claim 9 , wherein the IMT devices are a part of an FPGA backend. 15. A method, comprising: forming a first wiring line in a first metallic layer, wherein the first wiring line is to be coupled to a first programming access device and a routing block driver and receiver enabling device; forming a second wiring line in a second metallic layer that is vertically displaced from the second metallic layer, the second wiring line to be coupled to a second programming access device and a routing block driver and receiver enabling device; and forming an insulator-metal-transition (IMT) device coupled at the intersection of the first wiring line and the second wiring line, the IMT device coupled directly to the first wiring line and to the second wiring line. 16. The method of claim 15 , wherein the IMT device is configured to conduct electrical signals in a RLOW state. 17. The method of claim 15 , wherein the IMT device is a part of a RRAM free crosspoint. 18. The method of claim 15 , wherein the IMT device is configured to assume a state determined by a programming voltage. 19. The method of claim 15 , wherein the IMT device is configured to selectively couple inputs and outputs. 20. The method of claim 15 , wherein the IMT device is configured to hold a configuration state until it is reconfigured.
Assignees
Inventors
Classifications
Layouts of interconnections · CPC title
- H03K19/017581Primary
programmable · CPC title
Electricity · mapped topic
Electricity · mapped topic
- H01L45/1206Primary
Electricity · mapped topic
Patent family
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Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US11522130B2 cover?
- A routing structure is disclosed. A first wiring line coupled to a programming access device and a routing block driver and receiver enabling device and a second wiring line coupled to a programming access device and a routing block driver and receiver enabling device. An insulator-metal-transistor device that includes a top electrode, a middle electrode and a bottom electrode, coupled at the i…
- Who is the assignee on this patent?
- Intel Corp
- What technology area does this patent fall under?
- Primary CPC classification H03K19/017581. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Dec 06 2022 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).