High electron mobility transistor (HEMT) with RESURF junction

Patent metadata

Field	Value
Publication number	US-11522078-B2
Application number	US-201816629156-A
Country	US
Kind code	B2
Filing date	Jul 6, 2018
Priority date	Jul 7, 2017
Publication date	Dec 6, 2022
Grant date	Dec 6, 2022

Abstract

A High Electron Mobility Transistor (HEMT) having a reduced surface field (RESURF) junction is provided. The HEMT includes a source electrode at a first end and a drain electrode at a second end. A gate electrode is provided between the source electrode and the drain electrode. A reduced surface field (RESURF) junction extends from the first end to the second end. The gate electrode is provided above the RESURF junction. A buried channel layer is formed in the RESURF junction on application of a positive voltage at the gate electrode. The RESURF junction includes an n-type Gallium nitride (GaN) layer and a p-type GaN layer. The n-type GaN layer is provided between the p-type GaN layer and the gate electrode.

First claim

We claim:

1. A High Electron Mobility Transistor (HEMT) comprising:
a source electrode at a first end;
a drain electrode at a second end;
a gate electrode provided between the source electrode and the drain electrode; and
a reduced surface field (RESURF) junction, wherein the RESURF junction extends from the first end to the second end, wherein the gate electrode is provided above the RESURF junction, wherein a three-dimensional (3-D) buried channel of electrons is formed in the RESURF junction on application of a positive voltage at the gate electrode, the RESURF junction comprising:
an n-type Gallium nitride (GaN) layer; and
a p-type GaN layer, wherein the n-type GaN layer is provided between the p-type GaN layer and the gate electrode.

2. The HEMT as claimed in claim 1 , wherein the RESURF junction comprises an unintentionally doped (UID)-GaN layer provided on the n-type GaN layer.

3. The HEMT as claimed in claim 2 , wherein the UID-GaN layer is provided below the 3-D buried channel of electrons, wherein the HEMT comprises a plurality of layers provided on the 3-D buried channel of electrons, and wherein the plurality of layers comprises:
an Aluminum nitride (AlN) layer provided on the 3-D buried channel of electrons;
an Aluminium gallium nitride (AlGaN) layer provided on the AN layer;
a GaN cap provided on the AlGaN layer; and
a passivation dielectric layer provided on the GaN cap, wherein the gate electrode extends substantially from the passivation dielectric layer into the n-type GaN layer, wherein the gate electrode is coated with a gate oxide.

4. The HEMT as claimed in claim 2 , wherein the UID-GaN layer is provided below the 3-D buried channel of electrons, wherein the HEMT comprises a plurality of layers provided on the 3-D buried channel of electrons, and wherein the plurality of layers comprises:
an Aluminum nitride (AlN) layer provided on the 3-D buried channel of electrons;
an Aluminium gallium nitride (AlGaN) layer provided on the AN layer;
a GaN cap provided on the AlGaN layer; and
a passivation dielectric layer provided on the GaN cap, wherein the gate electrode extends substantially from the passivation dielectric layer into the UID-GaN layer, wherein the gate electrode is coated with a gate oxide.

5. The HEMT as claimed in claim 2 , wherein the UID-GaN layer is provided below the 3-D buried channel of electrons, wherein the HEMT comprises a plurality of layers provided on the 3-D buried channel of electrons, and wherein the plurality of layers comprises:
an Aluminum nitride (AlN) layer provided on the 3-D buried channel of electrons;
an Aluminium gallium nitride (AlGaN) layer provided on the AlN layer;
a GaN cap provided on the AlGaN layer; and
a passivation dielectric layer provided on the GaN cap, wherein the gate electrode extends substantially from the passivation dielectric layer into the AlN layer.

6. The HEMT as claimed in claim 2 , wherein the UID-GaN layer is provided below the 3-D buried channel of electrons, wherein the HEMT comprises a plurality of layers provided on the 3-D buried channel of electrons, and wherein the plurality of layers comprises:
an Aluminum nitride (AlN) layer provided on the 3-D buried channel of electrons;
an Aluminium gallium nitride (AlGaN) layer provided on the AlN layer;
a GaN cap provided on the AlGaN layer;
a passivation dielectric layer provided on the GaN cap; and
an Inter-Layer Dielectric (ILD) is provided on the passivation dielectric layer, wherein the gate electrode extends from the ILD to the GaN cap, wherein the gate electrode comprises:
a gate metal;
a gate dielectric, wherein the gate metal is provided on the gate dielectric, wherein the gate metal and the gate dielectric are provided in the ILD; and
a p-GaN gate layer, wherein the gate dielectric is provided on the p-GaN layer and wherein the p-GaN gate layer extends from the passivation dielectric layer to the GaN cap.

7. The HEMT as claimed in claim 1 , wherein the 3-D buried channel of electrons is formed on the n-type GaN layer, wherein the 3-D buried channel of electrons comprises an etched portion substantially close to the source electrode, and wherein the gate electrode is provided substantially above the etched portion.

8. The HEMT as claimed in claim 7 , wherein the HEMT comprises a plurality of layers provided on the 3-D buried channel of electrons.

9. The HEMT as claimed in claim 8 , wherein the plurality of layers comprises:
an Aluminum nitride (AlN) layer provided on the 3-D buried channel of electrons;
an Aluminium gallium nitride (AlGaN) layer provided on the AN layer;
a GaN cap provided on the AlGaN layer; and
a passivation dielectric layer provided on the GaN cap, wherein the gate electrode extends substantially from the passivation dielectric layer into the n-type GaN layer, wherein the gate electrode is coated with a gate oxide.

10. The HEMT as claimed in claim 9 , wherein
an Inter-Layer Dielectric (ILD) is provided on the passivation dielectric layer;
a first field plate (FP) is provided in the ILD above the gate electrode; and
a second FP is provided on the ILD above the gate electrode, wherein the second FP extends over the source electrode at the first end.

11. The HEMT as claimed in claim 10 , wherein the p-type GaN layer extends beyond the source electrode into an extended portion and wherein a substrate contact is provided on the p-type GaN layer in the extended portion.

12. The HEMT as claimed in claim 11 , wherein a third FP is provided over the drain electrode at the second end.

13. The HEMT as claimed in claim 11 , wherein the second FP extends over the substrate contact.

14. The HEMT as claimed in claim 9 wherein the gate oxide is implanted with fluorine ions.

15. The HEMT as claimed in claim 1 , wherein the gate electrode is a Schottky gate.

Assignees

• Indian Inst Scient

Inventors

• Soman Rohith
• Soni Ankit
• Shrivastava Mayank
• Raghavan Srinivasan
• Bhat Navakant

Classifications

• H01L29/404

  Electricity · mapped topic

• H01L29/205

  Electricity · mapped topic

• H01L29/063

  Electricity · mapped topic

• H01L29/7786 Primary

  Electricity · mapped topic

• H01L29/2003

  Electricity · mapped topic