Gate etch back with reduced loading effect

Patent metadata

Field	Value
Publication number	US-11522065-B2
Application number	US-202117207425-A
Country	US
Kind code	B2
Filing date	Mar 19, 2021
Priority date	Nov 30, 2017
Publication date	Dec 6, 2022
Grant date	Dec 6, 2022

Abstract

A method includes following steps. First and second gate electrodes are formed over a substrate, with an ILD layer between the first and second gate electrodes. A first etch operation is performed to etch the first and second gate electrodes. A sacrificial layer is formed across the etched first and second gate electrodes and the ILD layer. A second etch operation is performed to etch the sacrificial layer and the etched the first and second gate electrodes.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate;
a first gate electrode over the substrate, the first gate electrode comprising a first fill metal and a first work function metal layer wrapping around the first fill metal, the first fill metal comprising a first concave top surface; and
a second gate electrode over the substrate and having a second fill metal and a second work function metal layer wrapping around the second fill metal, the second fill metal comprising a second concave top surface narrower than the first concave top surface,
wherein a height difference between top ends of the first and second work function metal layers is less than a height difference between top ends of the first and second fill metals.

2. The semiconductor device of claim 1 , wherein the first fill metal further comprises a convex portion around the first concave top surface.

3. The semiconductor device of claim 1 , wherein the first fill metal comprises two convex top surfaces on opposite sides of the first concave top surface.

4. The semiconductor device of claim 1 , wherein the second gate electrode is narrower than the first gate electrode.

5. The semiconductor device of claim 1 , wherein a top surface of the first fill metal is higher than a top surface of the second fill metal.

6. The semiconductor device of claim 1 , wherein the top end of the first fill metal is higher than the top end of the first work function metal layer.

7. The device of claim 6 , further comprising a first gate dielectric layer below the first gate electrode, wherein the top end of the first fill metal is higher than a top end of first gate dielectric layer.

8. The semiconductor device of claim 1 , wherein the top end of the second fill metal is lower than the top end of the second work function metal layer.

9. The semiconductor device of claim 8 , further comprising a second gate dielectric layer below the second gate electrode, wherein the top end of the second fill metal is lower than a top end of second gate dielectric layer.

10. The semiconductor device of claim 1 , further comprising a third gate electrode over the substrate, wherein the third gate electrode is narrower than the first and second gate electrode, and the third gate electrode is free of a material of the first and second fill metal.

11. A semiconductor device, comprising:
a substrate;
a first gate structure over the substrate, wherein the first gate structure comprising:
a first gate dielectric layer;
a first work function metal layer over the first gate dielectric layer; and
a first fill metal over the first work function metal layer;

a first dielectric cap layer over the first gate structure;
a second gate structure over the substrate, wherein the second gate structure comprising:
a second gate dielectric layer;
a second work function metal layer over the second gate dielectric layer; and
a second fill metal over the second work function metal layer, wherein a top surface of the second fill metal comprises convex portions and a concave portion between the convex portions; and

a second dielectric cap layer over the second gate structure, wherein the second dielectric cap layer is in contact with the convex portions and the concave portion of the top surface of the second fill metal.

12. The semiconductor device of claim 11 , wherein an entirety of a top surface of the first fill metal is concave.

13. The semiconductor device of claim 11 , wherein the concave portion of the top surface of the first fill metal is narrower than the concave portion of the top surface of the second fill metal.

14. The semiconductor device of claim 11 , wherein an interface between the second dielectric cap layer and the concave portion of the top surface of the second fill metal is higher than an interface between the first dielectric cap layer and a top surface of the first fill metal.

15. The semiconductor device of claim 11 , wherein the first dielectric cap layer is narrower than the second dielectric cap layer.

16. The semiconductor device of claim 11 , further comprising:
first gate spacers on opposite sidewalls of the first gate structure and on opposite sidewalls of the first dielectric cap layer; and
second gate spacers on opposite sidewalls of the second gate structure and on opposite sidewalls of the second dielectric cap layer.

17. A semiconductor device, comprising:
a substrate;
a first gate structure over the substrate, wherein the first gate structure comprising:
a first gate dielectric layer;
a first work function metal layer over the first gate dielectric layer; and
a first fill metal over the first work function metal layer;

a second gate structure over the substrate, wherein the second gate structure comprising:
a second gate dielectric layer;
a second work function metal layer over the second gate dielectric layer; and
a second fill metal over the second work function metal layer, wherein a top surface of the second fill metal is higher than a top surface of the first fill metal; and

a third gate structure over the substrate, wherein the third gate structure comprising:
a third gate dielectric layer; and
a third work function metal layer over the third gate dielectric layer, wherein the third gate structure is free of a material of the first fill metal and the second fill metal.

18. The semiconductor device of claim 17 , wherein third gate structure is narrower than the first and second gate structures.

19. The semiconductor device of claim 18 , wherein the first gate structure is narrower than the second gate structure.

20. The semiconductor device of claim 17 , wherein a top surface of the second fill metal comprises convex portions and a concave portion between the convex portions.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lo Yi-Chen
• Chang Jung-Hao
• Lin Li-Te
• Lin Pinyen

Classifications

• H10P72/0421

  for drying etching · CPC title

• H10P50/285

  of materials not containing Si, e.g. PZT or Al2O3 · CPC title

• H10P50/267

  using plasmas · CPC title

• H10P50/242

  of Group IV materials · CPC title

• H10P14/6339

  deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD · CPC title