Deep in memory architecture using resistive switches

Patent metadata

Field	Value
Publication number	US-11522012-B2
Application number	US-201816147091-A
Country	US
Kind code	B2
Filing date	Sep 28, 2018
Priority date	Sep 28, 2018
Publication date	Dec 6, 2022
Grant date	Dec 6, 2022

Abstract

A DIMA semiconductor structure is disclosed. The DIMA semiconductor structure includes a frontend including a semiconductor substrate, a transistor switch of a memory cell coupled to the semiconductor substrate and a computation circuit on the periphery of the frontend coupled to the semiconductor substrate. Additionally, the DIMA includes a backend that includes an RRAM component of the memory cell that is coupled to the transistor switch.

First claim

What is claimed is:

1. A deep in-memory architecture (DIMA) semiconductor structure, comprising:
a frontend that includes:
a semiconductor substrate;
a transistor switch of a memory cell coupled to the semiconductor substrate; and
a computation circuit on the periphery of the frontend coupled to the semiconductor substrate;

and,

a backend that includes:
an RRAM component of the memory cell that is coupled to the transistor switch; and

wherein the memory cell has a one transistor and one resistor (1T-1R) structure.

2. The DIMA semiconductor structure of claim 1 , wherein the RRAM component includes RRAM material coupled to a drain of the transistor.

3. The DIMA semiconductor structure of claim 1 , wherein the transistor includes a back gate coupled to an interlayer dielectric material.

4. The DIMA semiconductor structure of claim 3 , wherein the transistor includes a high-k dielectric layer coupled to the back gate.

5. The DIMA semiconductor structure of claim 4 , wherein the transistor includes channel material coupled to the high-k dielectric layer.

6. The DIMA semiconductor structure of claim 5 , wherein the transistor includes a capping layer coupled to the channel material.

7. A deep in-memory architecture (DIMA) semiconductor structure, comprising:
a frontend that includes:
a semiconductor substrate; and
a computation circuit coupled to the semiconductor substrate,

and,

a backend that includes:
an RRAM component of a memory cell; and
a transistor switch of the memory cell coupled to the RRAM component.

8. The DIMA semiconductor structure of claim 7 , wherein the memory cell has a 1T-1R structure.

9. The DIMA semiconductor structure of claim 7 , wherein the RRAM component includes RRAM material coupled to a drain of the transistor.

10. The DIMA semiconductor structure of claim 7 , wherein the transistor includes a back gate coupled to an interlayer dielectric material.

11. The DIMA semiconductor structure of claim 10 , wherein the transistor includes a high-k dielectric layer coupled to the back gate.

12. The DIMA semiconductor structure of claim 11 , wherein the transistor includes channel material coupled to the high-k dielectric layer.

13. The DIMA semiconductor structure of claim 12 , wherein the transistor includes a capping layer coupled to the channel material.

14. A method, comprising:
forming a frontend that includes:
forming a semiconductor substrate; and
forming a computation circuit coupled to the semiconductor substrate,

and,

forming a backend that includes:
forming an RRAM component of a memory cell; and

forming a transistor switch of the memory cell coupled to the RRAM component.

15. The method claim 14 , wherein the memory cell has a 1T-1R structure.

16. The method of claim 14 , wherein the RRAM component includes RRAM material coupled to a drain of the transistor.

17. The method of claim 14 , wherein the transistor includes a back gate coupled to an interlayer dielectric material.

18. The method of claim 17 , wherein the transistor includes a high-k dielectric layer coupled to the back gate.

19. The method of claim 18 , wherein the transistor includes channel material coupled to the high-k dielectric layer.

Assignees

• Intel Corp

Inventors

• Kavalieros Jack T
• Young Ian A
• Krishnamurthy Ram
• Pillarisetty Ravi
• Manipatruni Sasikanth
• Chen Gregory
• Yoo Hui Jae
• Le Van H
• Sharma Abhishek
• Kumar Raghavan
• Liu Huichu
• Knag Phil
• SUMBUL Huseyin

Classifications

• G11C8/10

  Decoders · CPC title

• G11C13/0021

  Auxiliary circuits · CPC title

• G11C13/0028

  Word-line or row circuits · CPC title

• G11C2213/33

  Material including silicon · CPC title

• G11C2213/31

  Material having complex metal oxide, e.g. perovskite structure · CPC title