Method to integrate DC and RF phase change switches into high-speed SiGe BiCMOS

Patent metadata

Field	Value
Publication number	US-11522010-B2
Application number	US-201916544212-A
Country	US
Kind code	B2
Filing date	Aug 19, 2019
Priority date	Aug 19, 2019
Publication date	Dec 6, 2022
Grant date	Dec 6, 2022

Abstract

A method of integrating a phase change switch (PCS) into a Bipolar (Bi)/Complementary Metal Oxide Semiconductor (CMOS) (BiCMOS) process, comprises providing a base structure including BiCMOS circuitry on a semiconductor substrate, and forming on the base structure a dielectric contact window layer having metal through-plugs that contact the BiCMOS circuitry. The method includes constructing the PCS on the contact window layer. The PCS includes: a phase change region, between ohmic contacts on the phase change region, to operate as a switch controlled by heat. The method further includes forming, on the contact window layer and the PCS, a stack of alternating patterned metal layers and dielectric layers that interconnect the patterned metal layers, such that the stack connects a first of the ohmic contacts to the BiCMOS circuitry and provides connections to a second of the ohmic contacts and to the resistive heater.

First claim

What is claimed is:

1. An integrated circuit (IC) comprising:
a base structure including Bipolar (Bi)/Complementary Metal Oxide Semiconductor (CMOS) (BiCMOS) circuitry constructed on a semiconductor substrate;
a dielectric layer only over a PCS region of the semiconductor substrate that is adjacent to the BiCMOS circuitry;
a contact window layer on the base structure and the dielectric layer, the contact window layer having metal through-plugs that contact the BiCMOS circuitry;
a phase change switch (PCS) constructed on the contact window layer over the PCS region, the PCS including: a phase change region, connected between spaced-apart ohmic contacts on the phase change region, configured to operate as an in-line switch connected between the ohmic contacts and that is controlled by heat applied to the phase change region; and a resistive heater, formed as a metal through-plug in the contact window layer over the PCS region and on the semiconductor layer, to generate the heat responsive to a control signal applied to spaced-apart heater ohmic contacts formed on top of the metal through-plug; and
a stack on the contact window layer and the PCS, the stack including alternating patterned metal layers and dielectric layers having metal through-plugs to interconnect the patterned metal layers, such that the stack connects a first of the ohmic contacts to the BiCMOS circuitry and provides respective connections to a second of the ohmic contacts and to the resistive heater.

2. The IC of claim 1 , wherein the PCS further includes:
a dielectric barrier layer on the metal through-plug configured to serve as the resistive heater; and
wherein the phase change region is on the dielectric barrier layer;
wherein the ohmic contacts are on correspondingly spaced-apart ends of the phase change region.

3. The IC of claim 1 , further comprising:
an insulating layer between the PCS region of the semiconductor substrate and the metal through-plug in the contact window layer over the PCS region.

4. The IC of claim 3 , wherein the PCS further includes:
a passivation layer on the phase change region between the ohmic contacts.

5. The IC of claim 1 , wherein the BiCMOS circuitry includes a heterojunction bipolar transistor (HBT) including a power terminal, a base, an emitter, and a collector, and the stack is configured to connect the first of the ohmic contacts to the power terminal, the base, the emitter, or the collector of the HBT.

6. The IC of claim 1 , wherein the phase change region comprises a layer of Germanium Telluride (GeTe).

7. The IC of claim 1 , wherein the contact window layer on the base structure and the PCS on the contact window layer are arranged to form a structure having no patterned metal layers and no dielectric layers with metal through-plugs therein between the PCS and the BiCMOS circuitry, except for the contact window layer.

Assignees

• Northrop Grumman Systems Corp

Inventors

• Shea Patrick B
• Young Robert M
• Chung Keith H
• Ezis Andris
• Wathuthanthri Ishan

Classifications

• H10D84/401

  Combinations of FETs or IGBTs with BJTs · CPC title

• H01L45/1608

  Electricity · mapped topic

• H01L45/06

  Electricity · mapped topic

• H01L45/144

  Electricity · mapped topic

• H01L45/126

  Electricity · mapped topic