Polar transmitter with feedthrough compensation

Patent metadata

Field	Value
Publication number	US-11516054-B2
Application number	US-202117351779-A
Country	US
Kind code	B2
Filing date	Jun 18, 2021
Priority date	Dec 21, 2018
Publication date	Nov 29, 2022
Grant date	Nov 29, 2022

Abstract

A circuit includes a polar transmitter to generate a radio frequency output from amplitude and phase signal components. The polar transmitter includes an amplifier to combine amplitude and phase signal components. A processor is coupled to the polar transmitter to provide the amplitude and phase signal components. The processor includes: a digital modulation circuit to generate a modulated digital signal including in-phase and quadrature signal components and a correction circuit to calculate and apply a complex digital offset for local oscillator feedthrough of the amplifier. The complex digital offset includes an in-phase offset correction factor and a quadrature offset correction factor.

First claim

What is claimed is:

1. A circuit comprising:
a polar transmitter configured to generate a radio frequency output based on an amplitude signal component received at an amplitude input and a phase signal component received at a phase input, the polar transmitter including an amplifier to combine amplitude and phase signal components;
a processor coupled to the polar transmitter, the processor configured to provide the amplitude signal component to the amplitude input and to provide the phase signal component to the phase input, the processor comprising:
a digital modulation circuit configured to generate a modulated digital signal including an in-phase signal component and a quadrature signal component for conversion to the amplitude signal component and the phase signal component; and
a correction circuit configured to calculate a complex digital offset and apply the complex digital offset to correct the amplitude signal component and the phase signal component for local oscillator feedthrough of the amplifier, the complex digital offset includes an in-phase offset correction factor and a quadrature offset correction factor.

2. The circuit of claim 1 , wherein the processor includes a first Coordinate Rotation Digital Computer (CORDIC) configured to convert the in-phase signal component and the quadrature signal component to an initial amplitude signal component and an initial phase signal component.

3. The circuit of claim 2 , wherein the correction circuit includes a second CORDIC configured to calculate a phase offset to the phase signal component.

4. The circuit of claim 3 , wherein the correction circuit further includes a multiplier configured to apply a gain correction factor and an adder configured to apply the in-phase offset correction factor, the multiplier and the adder between the first CORDIC and the second CORDIC.

5. The circuit of claim 1 , wherein the processor includes a Coordinate Rotation Digital Computer (CORDIC) configured to convert the in-phase signal component and the quadrature signal component to an initial amplitude signal component and an initial phase signal component in a first clock cycle, and to calculate a phase offset and provide the phase offset to an adder to apply the phase offset to the initial phase signal component to generate the phase signal component in a second clock cycle.

6. The circuit of claim 5 , wherein the processor further includes a multiplier and the adder coupled to an output of the CORDIC, the multiplier configured to apply a gain correction factor and the adder to apply the in-phase offset correction factor to the amplitude signal component to generate the output.

7. The circuit of claim 6 , wherein the CORDIC is configured to receive the output and generate the amplitude signal component in the second clock cycle.

8. The circuit of claim 1 , wherein the correction circuit includes a first Coordinate Rotation Digital Computer (CORDIC) configured to convert the modulated digital signal to a Sine component and a Cosine component, the correction circuit configured to apply correction to the Sine component and the Cosine component and generate a corrected in-phase signal component and a corrected quadrature signal component, the processor includes a second CORDIC configured to convert the corrected in-phase signal component and the corrected quadrature signal component to the amplitude signal component and the phase signal component.

9. The circuit of claim 8 , wherein the correction circuit includes a plurality of multipliers including a first multiplier configured to combine the in-phase offset correction factor and the Cosine component, a second multiplier configured to combine the in-phase offset correction factor and the Sine component, a third multiplier configured to combine the quadrature offset correction factor and the Cosine component, a fourth multiplier configured to combine the quadrature offset correction factor and the Sine component, a first adder configured to combine outputs of the first and fourth multipliers, and a second adder configured to combine outputs of the second and third multipliers.

10. The circuit of claim 9 , wherein the correction circuit further includes a fifth multiplier configured to combine the in-phase signal component and a gain factor, a third adder configured to combine outputs of the fifth multiplier and the first adder to generate the corrected in-phase signal component, a sixth multiplier configured to combine the quadrature signal component and the gain factor, and a fourth adder configured to combine the output of the sixth multiplier and the second adder to generate the corrected quadrature signal component.

11. A method comprising:
generating a modulated digital signal including an in-phase signal component and a quadrature signal component;
converting the modulated digital signal to an amplitude signal component and a phase signal component;
combining the amplitude signal component and the phase signal component in an amplifier to generate a radio frequency output;
calculating a complex digital offset to digitally correct for local oscillator feedthrough of the amplifier, the complex digital offset includes an in-phase offset correction factor and a quadrature offset correction factor; and
applying the complex digital offset to correct the amplitude signal component and the phase signal component.

12. The method of claim 11 , wherein the quadrature offset correction factor is applied by a Coordinate Rotation Digital Computer (CORDIC) generating a phase offset and an adder combining the phase offset with the phase signal component.

13. The method of claim 11 , wherein converting the modulated digital signal to the amplitude signal component and the phase signal component is performed by a first CORDIC and the complex digital offset is applied by a second CORDIC coupled to receive the amplitude signal component from the first CORDIC.

14. The method of claim 11 , wherein the converting of the modulated digital signal to the amplitude signal component and the phase signal component is performed by a Coordinate Rotation Digital Computer (CORDIC) in a first clock cycle and the quadrature offset correction factor is applied by the CORDIC in a second clock cycle.

15. The method of claim 14 , further comprising, in the first clock cycle, applying a gain correction factor and an in-phase correction factor to the amplitude signal component to generate an output, the CORDIC receiving the output and correcting the amplitude signal component in the second clock cycle.

16. The method of claim 11 , further comprising:
converting the modulated digital signal including the in-phase signal component and the quadrature signal component to Sine and Cosine components;
applying the complex digital offset to the Sine and Cosine components; and
converting the Sine and Cosine components back to the in-phase signal component and the quadrature signal component.

17. The method of claim 11 , wherein converting the modulated digital signal to Sine and Cosine components is performed by a first CORDIC and generating the amplitude signal component and the phase signal component is performed by a second CORDIC.

18. A system comprising:
a polar transmitter formed on a substrate, the polar transmitter configured to generate a radio frequency output from an amplitude signal component received at an amplitude input and a phase signal component received at a phase input, the polar transmitter including a variable gain amplifier configured to combine the amplitude signal component and the phase

Assignees

• Huawei Tech Co Ltd

Inventors

• Al-Qaq Wael
• Yu Xiaobao
• Zhang Zhihang
• Yi Min

Classifications

• H04L27/2092 Primary

  with digital generation of the modulated carrier (does not include the modulation of a digitally generated carrier) · CPC title

• H03D5/00

  Circuits for demodulating amplitude-modulated or angle-modulated oscillations at will (H03D9/00, H03D11/00 take precedence) · CPC title

• H03D7/165 Primary

  at least two frequency changers being located in different paths, e.g. in two paths with carriers in quadrature (combined with amplitude demodulation H03D1/2245, combined with angle demodulation H03D3/007; N-path filters H03H19/002) · CPC title

• H03C5/00

  Amplitude modulation and angle modulation produced simultaneously or at will by the same modulating signal (H03C7/00 takes precedence) · CPC title