Semiconductor packages and manufacturing methods thereof

US11515618B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11515618-B2
Application numberUS-202117227387-A
CountryUS
Kind codeB2
Filing dateApr 12, 2021
Priority dateMay 26, 2016
Publication dateNov 29, 2022
Grant dateNov 29, 2022

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A semiconductor package includes a semiconductor chip and a redistribution layer structure. The redistribution layer structure is arranged to form an antenna transmitter structure and an antenna receiver structure over the semiconductor chip, wherein patterns of the antenna receiver structure are located at different levels of the redistribution layer structure, and at least one pattern of the antenna transmitter structure is at the same level of the topmost patterns of the antenna receiver structure.

First claim

Opening claim text (preview).

What is claimed is: 1. A semiconductor package, comprising: a semiconductor chip; and a redistribution layer structure arranged to form an antenna receiver structure over the semiconductor chip, wherein the antenna receiver structure comprises a plurality of sensing electrodes and a plurality of enhancement patterns located at different levels of the redistribution layer structure. 2. The semiconductor package of claim 1 , wherein the redistribution layer structure is further arranged to form an antenna transmitter structure aside the antenna receiver structure. 3. The semiconductor package of claim 2 , wherein the antenna transmitter structure surrounds the antenna receiver structure. 4. The semiconductor package of claim 2 , wherein at least one pattern of the antenna transmitter structure is at the same level of the topmost patterns of the antenna receiver structure. 5. The semiconductor package of claim 2 , wherein the antenna transmitter structure has a ring shape, a bar shape, a spiral shape, a wave shape, a meandering shape or a combination thereof. 6. The semiconductor package of claim 2 , wherein from a top view, the antenna transmitter structure is outside of a chip region of the semiconductor chip, and the antenna receiver structure is within the chip region of the semiconductor chip. 7. The semiconductor package of claim 1 , wherein the sensing electrodes are located at a higher level of the redistribution layer structure, and the enhancement patterns are located at a lower level of the redistribution layer structure. 8. The semiconductor package of claim 1 , wherein the enhancement patterns are aligned with the sensing electrodes. 9. The semiconductor package of claim 1 , wherein the enhancement patterns are misaligned with the sensing electrodes. 10. The semiconductor package of claim 1 , wherein each of the sensing electrodes and the enhancement patterns of the antenna receiver structure has an island shape, a snake shape, a bar shape, a fishbone shape, a fence shape, a grid shape, a ring shape or a combination thereof. 11. The semiconductor package of claim 1 , wherein the semiconductor package is a fingerprint semiconductor package. 12. A semiconductor package, comprising: a semiconductor chip; a redistribution layer structure arranged to form a plurality of sensing patterns, an antenna transmitter structure and an antenna receiver structure; and a polymer layer disposed over the redistribution layer structure, wherein the polymer layer covers the antenna transmitter structure and the antenna receiver structure while exposes the sensing patterns. 13. The semiconductor package of claim 12 , wherein from a top view, the sensing patterns and the antenna transmitter structure are within a chip region of the semiconductor chip, and the antenna receiver structure is outside of the chip region of the semiconductor chip. 14. The semiconductor package of claim 12 , further comprising molecular linkers respectively covering the exposed surfaces of the sensing patterns. 15. The semiconductor package of claim 12 , wherein the antenna receiver structure is electrically connected to a through-via aside the semiconductor chip. 16. The semiconductor package of claim 12 , wherein each of the antenna transmitter structure and the antenna receiver structure has a bar shape, a spiral shape, a wave shape, a meandering shape or a combination thereof. 17. The semiconductor package of claim 12 , wherein each of the sensing patterns has a split-ring shape. 18. The semiconductor package of claim 12 , wherein the antenna transmitter structure and the antenna receiver structure are laterally aside a redistribution layer of the redistribution layer structure. 19. A method of forming a semiconductor package, comprising: providing a semiconductor chip; forming a redistribution layer and a plurality of sensing patterns over the semiconductor chip; and forming a polymer layer over the redistribution layer and forming a plurality of molecular linkers respectively over the plurality of sensing patterns. 20. The method of claim 19 , further comprising, during the step of forming the redistribution layer and the plurality of sensing patterns, forming an antenna transmitter structure and an antenna receiver structure at two sides of the plurality of sensing patterns.

Assignees

Inventors

Classifications

  • using temporary auxiliary substrates (H10W74/017 takes precedence) · CPC title

  • comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu · CPC title

  • relative to underlying supporting features, e.g. bond pads, RDLs or vias · CPC title

  • Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

  • for antennas · CPC title

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Frequently asked questions

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What does patent US11515618B2 cover?
A semiconductor package includes a semiconductor chip and a redistribution layer structure. The redistribution layer structure is arranged to form an antenna transmitter structure and an antenna receiver structure over the semiconductor chip, wherein patterns of the antenna receiver structure are located at different levels of the redistribution layer structure, and at least one pattern of the …
Who is the assignee on this patent?
Taiwan Semiconductor Mfg Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10W74/117. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Nov 29 2022 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).