Contacts to n-type transistors with X-valley layer over L-valley channels

Patent metadata

Field	Value
Publication number	US-11515420-B2
Application number	US-201716643927-A
Country	US
Kind code	B2
Filing date	Sep 29, 2017
Priority date	Sep 29, 2017
Publication date	Nov 29, 2022
Grant date	Nov 29, 2022

Abstract

An apparatus is provided which comprises: a first region over a substrate, wherein the first region comprises a first semiconductor material having a L-valley transport energy band structure, a second region in contact with the first region at a junction, wherein the second region comprises a second semiconductor material having a X-valley transport energy band structure, wherein a <111> crystal direction of one or more crystals of the first and second semiconductor materials are substantially orthogonal to the junction, and a metal adjacent to the second region, the metal conductively coupled to the first region through the junction. Other embodiments are also disclosed and claimed.

First claim

We claim:

1. An apparatus comprising:
a first region over a substrate, wherein the first region comprises a first semiconductor material having a L-valley transport energy band structure;
a second region in contact with the first region at a junction, wherein the second region comprises a second semiconductor material having a X-valley transport energy band structure, wherein a <111> crystal direction of one or more crystals of the first and second semiconductor materials are substantially orthogonal to the junction; and
a metal adjacent to the second region, the metal conductively coupled to the first region through the junction, wherein the substrate has cubic crystallinity, and wherein the junction is one of (A) substantially orthogonal to a (110) plane of the substrate, or (B) substantially parallel to a (111) plane of the substrate.

2. The apparatus of claim 1 , wherein the junction is substantially 45 degrees to a surface of the first region nearest a (100) plane of the substrate.

3. The apparatus of claim 1 , wherein the junction is substantially orthogonal to a surface of the first region nearest a (110) plane of the substrate.

4. The apparatus of claim 1 , wherein the junction is substantially parallel to a surface of the first region nearest a (111) plane of the substrate.

5. The apparatus of claim 1 , wherein the first semiconductor material comprises germanium or indium, gallium, and arsenic, and wherein the junction comprises a facet of the first semiconductor material.

6. The apparatus of claim 1 , wherein the second semiconductor material comprises at least one of silicon or germanium.

7. The apparatus of claim 1 , wherein the second semiconductor material comprises silicon and germanium with a graded concentration of germanium, the graded concentration comprising a greater than 50% concentration of germanium adjacent the junction.

8. The apparatus of claim 1 , wherein the second semiconductor material comprises silicon and germanium with a graded concentration of germanium.

9. A NMOS device comprising:
a channel region over a substrate, wherein the channel region comprises a first semiconductor material having a L-valley transport energy band structure;
a gate stack over the channel region;
a source region in contact with the channel region at a junction, wherein the source region comprises a second semiconductor material having a X-valley transport energy band structure, wherein a <111> crystal direction of one or more crystals of the first and second semiconductor materials are substantially orthogonal to the junction; and
a metal adjacent to the source region, the metal conductively coupled to the channel region through the junction,
wherein the second semiconductor material comprises silicon and germanium, and the germanium concentration is greater than 50% adjacent the junction.

10. The NMOS device of claim 9 , wherein the substrate has cubic crystallinity and wherein the junction is substantially 45 degrees to a surface of the first region nearest a (100) plane of the substrate.

11. The NMOS device of claim 9 , wherein the substrate has cubic crystallinity and wherein the junction is substantially orthogonal to a surface of the first region nearest a (110) plane of the substrate.

12. The NMOS device of claim 9 , wherein the substrate has cubic crystallinity and wherein the junction is substantially parallel to a surface of the first region nearest a (111) plane of the substrate.

13. The NMOS device of claim 9 , wherein the first semiconductor material comprises germanium or indium, gallium, and arsenic, and wherein the junction comprises a facet of the first semiconductor material.

14. The NMOS device of claim 9 , wherein the concentration of germanium within the second semiconductor material is graded.

15. A system comprising:
a display subsystem;
a wireless communication interface; and
an integrated circuit device, the integrated circuit device comprising:
a channel region over a substrate, wherein the channel region comprises a first semiconductor material having a L-valley transport energy band structure;
a gate stack on the channel region;
a source region in contact with the channel region at a junction, wherein the source region comprises a second semiconductor material having a X-valley transport energy band structure, wherein a <111> crystal direction of one or more crystals of the first and second semiconductor materials are substantially orthogonal to the junction, wherein the second semiconductor material comprises silicon and germanium with a graded concentration of germanium; and
a metal adjacent to the source region, the metal conductively coupled to the channel region through the junction.

16. The system of claim 15 , wherein the substrate has cubic crystallinity and wherein the junction is substantially 45 degrees to a surface of the first region nearest a (100) plane of the substrate.

17. The system of claim 15 , wherein the substrate has cubic crystallinity and wherein the junction is substantially orthogonal to a surface of the first region nearest a (110) plane of the substrate.

18. The system of claim 15 , wherein the substrate has cubic crystallinity and wherein the junction is substantially parallel to a surface of the first region nearest a (111) plane of the substrate, wherein the junction comprises a facet of the first semiconductor material.

Assignees

• Intel Corp

Inventors

• Crum Dax M
• Weber Cory E
• Mehandru Rishabh
• Kennel Harold
• Chu-Kung Benjamin

Classifications

• H10P14/3466

  Crystal orientation · CPC title

• H10P14/3421

  Arsenides · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10D64/0116

  to Group III-V semiconductors · CPC title

• H10D64/0111

  to Group IV semiconductors · CPC title