Array substrate, manufacturing method thereof, and display device

Patent metadata

Field	Value
Publication number	US-11515341-B2
Application number	US-202016932902-A
Country	US
Kind code	B2
Filing date	Jul 20, 2020
Priority date	Sep 25, 2019
Publication date	Nov 29, 2022
Grant date	Nov 29, 2022

Abstract

The present application relates to the field of display technology and, in particular, to an array substrate, a manufacturing method of the array substrate, and a display device. An array substrate comprises: a base substrate having a pixel display area and a gate drive circuit area; a first thin film transistor formed in the pixel display area, the first thin film transistor comprising a first gate insulating layer; a second thin film transistor formed in the gate drive circuit area, the second thin film transistor comprising a second gate insulating layer, where a thickness of the second gate insulating layer is smaller than a thickness of the first gate insulating layer.

First claim

What is claimed is:

1. A manufacturing method of an array substrate, comprising:
providing a base substrate, the base substrate having a pixel display area and a gate drive circuit area; and
forming a first thin film transistor located in the pixel display area and a second thin film transistor located in the gate drive circuit area by:
forming a first gate of the first thin film transistor and a second gate of the second thin film transistor;
forming a photoresist layer covering the gate insulating film, and exposing and developing the photoresist layer using a gray-scale mask to form a photolithography pattern, wherein, the photolithography pattern comprises a first photolithography portion located in the pixel display area, a second photolithography portion located in the gate drive circuit area, and a thickness of the second photolithography portion is smaller than a thickness of the first photolithography portion;
removing the second photolithography portion and performing etching processing at a portion of the gate insulating film aligned to the gate drive circuit area, to form a first gate insulating layer and a second gate insulating layer;
forming a first active layer of the first thin film transistor on the first gate insulating layer and a second active layer of the second thin film transistor on the second gate insulating layer; and
forming a first source/drain of the first thin film transistor on the first active layer and a second source/drain of the second thin film transistor on the second active layer;

wherein the first thin film transistor comprises the first gate insulating layer, the second thin film transistor comprises the second gate insulating layer, and a thickness of the second gate insulating layer is smaller than a thickness of the first gate insulating layer.

2. The manufacturing method according to claim 1 , wherein removing the second photolithography portion and performing the etching processing at the portion of the gate insulating film aligned to the gate drive circuit area, comprises:
using reaction gas to perform ashing processing on the second photolithography portion, to remove the second photolithography portion; and
continuing to use the reaction gas to perform the dry etching processing at a portion of the gate insulating film aligned to the second photolithography portion, to etch away a part of a thickness of the portion of the gate insulating film aligned to the second photolithography portion, to form the first gate insulating layer and the second gate insulating layer.

3. The manufacturing method according to claim 2 , wherein:
the gate insulating film is made of one or more of silicon oxide, silicon nitride, and silicon oxynitride;
the photoresist layer is a positive photoresist; and
the reaction gas comprises sulfur hexafluoride and oxygen, and a flow ratio of the sulfur hexafluoride to the oxygen is 1:200 to 1:10.

4. The manufacturing method according to claim 2 , wherein a flow rate of the sulfur hexafluoride is 100 sccm to 1000 sccm, and a flow rate of the oxygen is 10000 sccm to 20000 sccm.

5. A manufacturing method for manufacturing an array substrate, comprising:
providing a base substrate, the base substrate having a pixel display area and a gate drive circuit area;
forming a first thin film transistor located in the pixel display area and a second thin film transistor located in the gate drive circuit area, wherein the first thin film transistor comprises a first gate insulating layer, the second thin film transistor comprises a second gate insulating layer, and a thickness of the second gate insulating layer is smaller than a thickness of the first gate insulating layer, and wherein the base substrate further comprises a wiring area;
forming a first gate of the first thin film transistor and a second gate of the second thin film transistor, and meanwhile, further forming a third gate located in the wiring area, the third gate being connected to the second gate; and forming a gate insulating film covering the first gate, the second gate, and the third gate;
forming a photoresist layer covering the gate insulating film, and exposing and developing the photoresist layer using a gray-scale mask to form a photolithography pattern, wherein, the photolithography pattern comprises a first photolithography portion located in the pixel display area, a second photolithography portion located in the gate drive circuit area, and a third photolithography portion located in the wiring area, a thickness of the second photolithography portion is smaller than a thickness of the first photolithography portion, and the third photolithography portion has a through hole aligned to the third gate;
removing the second photolithography portion and performing etching processing at a portion of the gate insulating film aligned to the gate drive circuit area and the through hole, to form the first gate insulating layer and the second gate insulating layer, and meanwhile, further form a third gate insulating layer covering a third gate, the third gate insulating layer having a via hole to expose the third gate;
forming a first active layer of the first thin film transistor on the first gate insulating layer and a second active layer of the second thin film transistor on the second gate insulating layer; and
forming a first source/drain of the first thin film transistor on the first active layer and a second source/drain of the second thin film transistor on the second active layer, and meanwhile, further forming a transition line on the third gate insulating layer, the transition line being connected to the second source/drain, and one end of the transition line being located in the via hole and connected to the third gate.

6. The manufacturing method according to claim 5 , wherein removing the second photolithography portion and performing the etching processing at the portion of the gate insulating film aligned to the gate drive circuit area and the through hole further comprises:
using reaction gas to simultaneously perform ashing processing on the second photolithography portion and dry etching processing at a portion of the gate insulating film aligned to the through hole, to remove the second photolithography portion and etch away a part of a thickness of the portion of the gate insulating film aligned to the through hole; and
continuing to use the reaction gas to simultaneously perform the dry etching processing at a portion of the gate insulating film aligned to the second photolithography portion and the portion of the gate insulating film aligned to the through hole, to etch away a part of a thickness of the portion of the gate insulating film aligned to the second photolithography portion, and completely etch away the portion of the gate insulating film aligned to the through hole, to form the first gate insulating layer, the second gate insulating layer, and the third gate insulating layer.

7. The manufacturing method according to claim 6 , wherein:
the gate insulating film is made of one or more of silicon oxide, silicon nitride, and silicon oxynitride;
the photoresist layer is a positive photoresist; and
the reaction gas comprises sulfur hexafluoride and oxygen, and a flow ratio of the sulfur hexafluoride to the oxygen is 1:200 to 1:10.

8. The manufacturing method according to claim 7 , wherein a flow rate of the sulfur hexafluoride is 100 sccm to 1000 sccm, and a flow rate of the oxygen is 10000 sccm to 20000 sccm.

Assignees

• Fuzhou Boe Optoelectronics Tech Co Ltd
• Boe Technology Group Co Ltd
• Beijing Boe Technology Dev Co Ltd

Inventors

• Lin Bin
• Zeng Yong
• Huo Yazhou
• Wu Rong
• Chen Zhouyu
• Li Liangliang

Classifications

• H01L27/1288

  Electricity · mapped topic

• H01L27/1248

  Electricity · mapped topic

• H01L27/1225

  Electricity · mapped topic

• H01L27/1259

  Electricity · mapped topic

• H01L27/1237

  Electricity · mapped topic