Display apparatus having a stepped part

Patent metadata

Field	Value
Publication number	US-2016322402-A1
Application number	US-201615091624-A
Country	US
Kind code	A1
Filing date	Apr 6, 2016
Priority date	Apr 30, 2015
Publication date	Nov 3, 2016
Grant date	—

Abstract

Provided is a display apparatus including a substrate and a semiconductor layer including first and second semiconductor layers. A first gate insulating layer is formed on the semiconductor layer. A first gate wiring overlapping the first semiconductor layer is formed on the first gate insulating layer. A second gate insulating layer is formed on the first gate wiring. A second gate wiring overlapping the second semiconductor layer is formed on the second gate insulating layer. A third gate insulating layer covers the second gate wiring. A driving voltage line intersecting the first and second gate wirings is formed on the third gate insulating layer. A data line intersecting the first and second gate wirings is formed on the third gate insulating layer. A short circuit protection area is formed between the first gate wiring, the second gate wiring, the driving voltage line and the data line.

First claim

What is claimed is:

1 . A display apparatus, comprising:
a substrate; a semiconductor layer formed on the substrate, wherein the semiconductor layer includes a first semiconductor layer and a second semiconductor layer spaced apart from the first semiconductor layer; a first gate insulating layer formed on the semiconductor layer; a first gate wiring formed on the first gate insulating layer, wherein the first gate wiring overlaps the first semiconductor layer; a second gate insulating layer formed on the first gate wiring; a second gate wiring formed on the second gate insulating layer, wherein the second gate wiring overlaps the second semiconductor layer; a third gate insulating layer covering the second gate wiring; a driving voltage line formed on the third gate insulating layer, wherein the driving voltage line intersects the first gate wiring and the second gate wiring; a data line formed on the third gate insulating layer, wherein the data line intersects the first gate wiring and the second gate wiring; and a short circuit protection area formed between the first gate wiring and the second gate wiring, wherein the short circuit protection area is formed between the driving voltage line and the data line, and wherein an interval between the first gate wiring and the second gate wiring in the short circuit protection area is larger than an interval between the first gate wiring and the second gate wiring outside of the short circuit protection area.

2 . The display apparatus of claim 1 , wherein the interval between the first gate wiring and the second gate wiring in the short circuit protection area is an average value of the interval between the first gate wiring and the second gate wiring in the short circuit protection area.

3 . The display apparatus of claim 1 , wherein the interval between the first gate wiring and the second gate wiring in the short circuit protection area is a maximum value of the interval between the first gate wiring and the second gate wiring in the short circuit protection area.

4 . The display apparatus of claim 1 , further comprising:
a lower electrode of a capacitor formed on the second gate insulating layer; and an upper electrode of the capacitor formed on the third gate insulating layer.

5 . The display apparatus of claim 1 , further comprising:
a buffer layer formed between the substrate and the semiconductor layer.

6 . A display apparatus, comprising:
a substrate; a semiconductor layer formed on the substrate, wherein the semiconductor layer includes a first semiconductor layer and a second semiconductor layer spaced apart from the first semiconductor layer; a first gate insulating layer formed on the semiconductor layer; a first gate wiring formed on the first gate insulating layer, wherein the first gate wiring overlaps the first semiconductor layer; a second gate insulating layer formed on the first gate wiring; a second gate wiring formed on the second gate insulating layer, wherein the second gate wiring overlaps the second semiconductor layer; a third gate insulating layer covering the second gate wiring; a driving voltage line formed on the third gate insulating layer, wherein the driving voltage line intersects the first gate wiring and the second gate wiring; a data line formed on the third gate insulating layer, wherein the data line intersects the first gate wiring and the second gate wiring; a short circuit protection area formed between the first gate wiring and the second gate wiring, wherein the short circuit protection area is formed between the driving voltage line and the data line; and a stepped part protruding from any one of the first gate wiring and the second gate wiring formed in the short circuit protection area.

7 . The display apparatus of claim 6 , wherein the stepped part protrudes from the first gate wiring toward the second gate wiring to be disposed under the second gate wiring, and wherein the stepped part forms a step on the second gate wiring and the third gate insulating layer.

8 . The display apparatus of claim 6 , wherein the stepped part protrudes from the second gate wiring toward the first gate wiring to be disposed on the first gate wiring, and wherein the stepped part forms a step on the second gate wiring and the third gate insulating layer.

9 . The display apparatus of claim 6 , wherein the stepped part includes a same material as at least one of the first gate wiring and the second gate wiring.

10 . The display apparatus of claim 6 , further comprising:
a lower electrode of a capacitor formed on the second gate insulating layer; and an upper electrode of the capacitor formed on the third gate insulating layer.

11 . The display apparatus of claim 6 , further comprising:
a buffer layer formed between the substrate and the semiconductor layer.

12 . The display apparatus of claim 1 , wherein the interval between the first gate wiring and the second gate wiring varies within the short circuit protection area.

13 . The display apparatus of claim 1 , wherein the interval between the first gate wiring and the second gate wiring is constant within the short circuit protection area.

14 . The display apparatus of claim 6 , wherein the stepped part is formed between a data line and a driving voltage line.

Assignees

• Samsung Display Co Ltd

Inventors

• Kim Hyo Jin
• Lee Won Kyu
• Tae Seung Gyu

Classifications

• H10D86/451

  characterised by the compositions or shapes of the interlayer dielectrics · CPC title

• H10D86/443

  adapted for preventing breakage, peeling or short circuiting · CPC title

• H10D86/423 Primary

  comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO · CPC title

• H10D86/481

  integrated with passive devices, e.g. auxiliary capacitors · CPC title

• H10D86/60 Primary

  wherein the TFTs are in active matrices · CPC title