Semiconductor memory device

Patent metadata

Field	Value
Publication number	US-11515316-B2
Application number	US-202017103872-A
Country	US
Kind code	B2
Filing date	Nov 24, 2020
Priority date	Nov 5, 2020
Publication date	Nov 29, 2022
Grant date	Nov 29, 2022

Abstract

A semiconductor memory device includes a select transistor and a floating gate transistor on a substrate. The select transistor includes a select gate, a select gate oxide layer and a drain doping region. The floating gate transistor includes a floating gate, a floating gate oxide layer, a source doping region, a first tunnel doping region and a second tunnel doping region under the floating gate, a first tunnel oxide layer on the first tunnel doping region, and a second tunnel oxide layer on the second tunnel doping region. The floating gate oxide layer is disposed between the first tunnel oxide layer and the second tunnel oxide layer. A lightly doped diffusion region surrounds the source doping region and the second tunnel doping region.

First claim

What is claimed is:

1. A semiconductor memory device, comprising:
a substrate having a first conductivity type, wherein the substrate comprises a first active area surrounded by a trench isolation region;
a select transistor disposed on the first active area, wherein the select transistor comprises a select gate, a select gate oxide layer under the select gate, and a drain doping region having a second conductivity type disposed adjacent to the select gate;
a floating gate transistor disposed on the first active area and in proximity to the select transistor, wherein the floating gate transistor comprises a floating gate, a floating gate oxide layer under the floating gate, a source doping region having the second conductivity type disposed adjacent to the floating gate, a first tunnel doping region under the floating gate and between the floating gate oxide layer and the source doping region, a first tunnel oxide layer on the first tunnel doping region, a second tunnel doping region under the floating gate and between the floating gate oxide layer and the select gate, and a second tunnel oxide layer on the second tunnel doping region, wherein the first tunnel doping region is contiguous with the source doping region; and
a lightly doped diffusion region having the second conductivity type surrounding the source doping region and the first tunnel doping region.

2. The semiconductor memory device according to claim 1 , wherein the first conductivity type is P type and the second conductivity type is N type.

3. The semiconductor memory device according to claim 2 , wherein the first tunnel doping region and the second tunnel doping region are N + doping regions.

4. The semiconductor memory device according to claim 1 , wherein the lightly doped diffusion region is an N − doping region.

5. The semiconductor memory device according to claim 1 , wherein the select gate oxide layer has a thickness smaller than that of the floating gate oxide layer.

6. The semiconductor memory device according to claim 5 , wherein the floating gate oxide layer has a thickness ranging between 200 angstroms and 380 angstroms.

7. The semiconductor memory device according to claim 6 , wherein the select gate oxide layer has a thickness ranging between 50 angstroms and 130 angstroms.

8. The semiconductor memory device according to claim 1 , wherein the first tunnel oxide layer is disposed directly on the first tunnel doping region, and wherein the first tunnel oxide layer has a thickness smaller than that of the floating gate oxide layer.

9. The semiconductor memory device according to claim 8 , wherein the second tunnel oxide layer is disposed directly on the second tunnel doping region, and wherein the second tunnel oxide layer has a thickness smaller than that of the floating gate oxide layer.

10. The semiconductor memory device according to claim 9 , wherein first tunnel oxide layer and the second tunnel oxide layer have a thickness ranging between 70 angstroms and 95 angstroms.

11. The semiconductor memory device according to claim 1 further comprising:
a first peripheral gate oxide layer that is contiguous with the first tunnel oxide layer, wherein the first peripheral gate oxide layer has a thickness that is greater than that of the first tunnel oxide layer.

12. The semiconductor memory device according to claim 11 , wherein the floating gate has a first edge that is aligned with an outer edge of the first peripheral gate oxide layer.

13. The semiconductor memory device according to claim 12 further comprising:
a second peripheral gate oxide layer that is contiguous with the second tunnel oxide layer, wherein the second peripheral gate oxide layer has a thickness that is greater than that of the second tunnel oxide layer.

14. The semiconductor memory device according to claim 13 , wherein the floating gate has a second edge that is aligned with an outer edge of the second peripheral gate oxide layer.

15. The semiconductor memory device according to claim 1 further comprising:
a second active area in proximity to the first active area, wherein the first active area is isolated from the second active area by the trench isolation region, wherein the floating gate extends to the second active area from the first active area; and
a control gate doping region having the second conductivity type within the second active area.

16. The semiconductor memory device according to claim 15 , wherein the control gate doping region is an N + doping region.

17. The semiconductor memory device according to claim 15 , wherein the control gate doping region is capacitively coupled to the floating gate.

18. The semiconductor memory device according to claim 15 , wherein the lightly doped diffusion region surrounds the control gate doping region.

Assignees

• United Microelectronics Corp

Inventors

• Chen Tzu-Ping

Classifications

• H01L27/11524 Primary

  Electricity · mapped topic

• H01L27/11558

  Electricity · mapped topic

• H01L27/11519

  Electricity · mapped topic

• H10D30/683

  programmed by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling · CPC title

• H10B41/35 Primary

  with a cell select transistor, e.g. NAND · CPC title