Integrated circuit, package structure, and manufacturing method of package structure

Patent metadata

Field	Value
Publication number	US-11515276-B2
Application number	US-202017006879-A
Country	US
Kind code	B2
Filing date	Aug 30, 2020
Priority date	Aug 30, 2020
Publication date	Nov 29, 2022
Grant date	Nov 29, 2022

Abstract

An integrated circuit includes a semiconductor substrate, contact pads, testing pads, conductive posts, and dummy posts. The contact pads and the testing pads are distributed over the semiconductor substrate. The conductive posts are disposed on the contact pads. The dummy posts are disposed on the testing pads. A height of the conductive posts is greater than a height of the dummy posts.

First claim

What is claimed is:

1. An integrated circuit, comprising:
a semiconductor substrate;
contact pads and testing pads distributed over the semiconductor substrate;
conductive posts disposed on the contact pads; and
dummy posts disposed on the testing pads, wherein a height of the conductive posts is greater than a height of the dummy posts, and the dummy posts are electrically floating.

2. The integrated circuit of claim 1 , further comprising a protection layer covering the conductive posts and the dummy posts.

3. The integrated circuit of claim 1 , wherein a size of the testing pads is greater than a size of the contact pads.

4. The integrated circuit of claim 1 , wherein a ratio of a width of the testing pads to a width of the contact pads ranges between 2:1 and 5:1.

5. The integrated circuit of claim 1 , wherein each dummy post comprises a seed layer and a conductive material layer, the seed layer covers the testing pad and the conductive material layer is disposed on the seed layer.

6. The integrated circuit of claim 1 , further comprising functional components and testing components embedded in the semiconductor substrate, wherein the conductive posts and the contact pads are electrically connected to the functional components, and the dummy posts and the testing pads are electrically connected to the testing components.

7. The integrated circuit of claim 1 , wherein a width of the dummy posts is greater than a width of the conductive posts.

8. A package structure, comprising:
an integrated circuit, comprising:
a semiconductor substrate;
contact pads and testing pads distributed over the semiconductor substrate;
conductive posts disposed on the contact pads; and
dummy posts disposed on the testing pads, wherein the dummy posts are electrically floating;

an encapsulant laterally encapsulating the integrated circuit; and
a redistribution structure disposed on the integrated circuit and the encapsulant, wherein the conductive posts are electrically connected to the redistribution structure.

9. The package structure of claim 8 , wherein a height of the conductive posts is greater than a height of the dummy posts.

10. The package structure of claim 8 , wherein a size of the testing pads is greater than a size of the contact pads.

11. The package structure of claim 8 , wherein the dummy posts are electrically insulated from the redistribution structure.

12. The package structure of claim 8 , wherein the conductive posts are directly in contact with the redistribution structure, and the dummy posts are spaced apart from the redistribution structure.

13. The package structure of claim 8 , wherein a width of the dummy posts is greater than a width of the conductive posts.

14. The package structure of claim 8 , wherein the integrated circuit further comprises a protection layer, the protection layer covers sidewalls of the conductive posts, and the protection layer covers both sidewalls and top surfaces of the dummy posts.

15. The package structure of claim 8 , wherein each dummy post comprises a seed layer and a conductive material layer, the seed layer covers the testing pad and the conductive material layer is disposed on the seed layer.

16. A manufacturing method of a package structure, comprising:
forming an integrated circuit, comprising:
providing a semiconductor wafer;
forming contact pads and testing pads over the semiconductor wafer;
forming a passivation layer over the contact pads and the testing pads, wherein the passivation layer partially exposes each contact pad and each testing pad;

forming conductive posts on the contact pads; and
forming dummy posts on the testing pads, wherein the dummy posts are formed to be shorter than the conductive posts, and the dummy posts are formed to be electrically floating;

encapsulating the integrated circuit by an encapsulant; and
forming a redistribution structure over the integrated circuit and the encapsulant such that the conductive posts are electrically connected to the redistribution structure.

17. The method of claim 16 , further comprising:
performing a wafer testing operation on the testing pads prior to the formation of the dummy posts.

18. The method of claim 16 , wherein the conductive posts and the dummy posts are simultaneously formed.

19. The method of claim 16 , wherein forming the conductive posts and the dummy posts comprises:
depositing a seed layer on the passivation layer, the contact pads, and the testing pads;
forming a photoresist layer over the seed layer, wherein the photoresist layer comprises openings, and the openings partially expose the seed layer above the contact pads and the testing pads;
filling a conductive material layer into the openings of the photoresist layer;
removing the photoresist layer and the seed layer uncovered by the conductive material layer to form the conductive posts and the dummy posts.

20. The method of claim 16 , wherein the conductive posts are formed to be slimmer than the dummy posts.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Kuo Hung-Jui
• Tsai Hui-Jung
• Chang Tai-Min
• Wang Chia-Wei

Classifications

• H10W90/00

  Package configurations · CPC title

• H10W74/10

  characterised by their shape or disposition · CPC title

• H10W74/01

  Manufacture or treatment · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title