Method for manufacturing insulating layer for semiconductor package and insulating layer for semiconductor package using the same

US11515245B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11515245-B2
Application numberUS-201816767872-A
CountryUS
Kind codeB2
Filing dateDec 12, 2018
Priority dateJan 10, 2018
Publication dateNov 29, 2022
Grant dateNov 29, 2022

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

The present invention relates to a method for manufacturing an insulating layer for a semiconductor package which can improve reliability and have excellent heat resistance by removing pores generated in the insulating layer during manufacture of an insulating layer for a semiconductor package using magnetic characteristics, and an insulating layer for a semiconductor package obtained using the method for manufacturing the insulating layer for a semiconductor package.

First claim

Opening claim text (preview).

The invention claimed is: 1. A method for manufacturing an insulating layer for a semiconductor package comprising the steps of: a first step of forming, on a circuit board, a thermosetting resin film containing a heat-curable binder resin, a heat curing catalyst, and 30% to 90% by weight of a metal grafting porous structure based on the total weight of the thermosetting resin film; and a second step of heat curing the thermosetting resin film to prepare the insulating layer on the circuit board, wherein in at least one of the first step and the second step, a magnetic field of 0.1 T to 1 T is applied to the thermosetting resin film. 2. The method for manufacturing an insulating layer for a semiconductor package according to claim 1 , wherein, when the magnetic field of 0.1 T to 1 T is applied to the thermosetting resin film, the metal grafting porous structure contained in the thermosetting resin film has a Moment/Mass measurement value of 0.6 emu/g to 2.0 emu/g as measured using a vibration sample magnetometer. 3. The method for manufacturing an insulating layer for a semiconductor package according to claim 1 , wherein the thermosetting resin film further includes pores having an average diameter of 1.2 μm or more before the magnetic field of 0.1 T to 1 T is applied to the thermosetting resin film. 4. The method for manufacturing an insulating layer for a semiconductor package according to claim 1 , wherein the thermosetting resin film includes pores having an average diameter of 1 μm or less after the magnetic field of 0.1 T to 1 T is applied to the thermosetting resin film. 5. The method for manufacturing an insulating layer for a semiconductor package according to claim 1 , wherein the metal grafting porous structure is a structure having a metal grafted to a molecular sieve containing silicate. 6. The method for manufacturing an insulating layer for a semiconductor package according to claim 5 , wherein the molecular sieve containing silicate includes a zeolite, a silica molecular sieve having fine pores uniformly formed or a mixture thereof. 7. The method for manufacturing an insulating layer for a semiconductor package according to claim 6 , wherein the zeolite is one or more selected from the group consisting of mordenite, ferrierite, ZSM-5, β-zeolite, Ga-silicate, Ti-silicate, Fe-silicate, and Mn-silicate. 8. The method for manufacturing an insulating layer for a semiconductor package according to claim 6 , wherein the silica molecular sieve includes one or more selected from the group consisting of MCM-22, MCM-41, and MCM-48. 9. The method for manufacturing an insulating layer for a semiconductor package according to claim 5 , wherein the metal is one or more selected from the group consisting of nickel, copper, iron, and aluminum. 10. The method for manufacturing an insulating layer for a semiconductor package according to claim 1 , wherein the metal grafting porous structure includes a structure having a metal grafted to a silica molecular sieve in which fine pores having a diameter of 1 nm to 30 nm are uniformed formed. 11. The method for manufacturing an insulating layer for a semiconductor package according to claim 1 , wherein the metal grafting porous structure is one or more selected from the group consisting of Ni/MCM-41, Fe/MCM-41, and Cu/MCM-41. 12. The method for manufacturing an insulating layer for a semiconductor package according to claim 1 , wherein the metal grafting porous structure has a particle diameter of 1 μm or less. 13. The method for manufacturing an insulating layer for a semiconductor package according to claim 1 , wherein the thermosetting resin film contains 1% to 65% by weight of the heat-curable binder resin, and 0.1% to 20% by weight of the heat curing catalyst based on the total weight of the thermosetting resin film. 14. The method for manufacturing an insulating layer for a semiconductor package according to claim 1 , wherein the heat-curable binder resin is a thermosetting resin containing one or more functional groups selected from the group consisting of an epoxy group, an oxetanyl group, a cyclic ether group, and a cyclic thioether group.

Assignees

Inventors

Classifications

  • by heating, with or without pressure · CPC title

  • Flexible insulating substrates · CPC title

  • Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

  • H10W70/69Primary

    Insulating materials thereof · CPC title

  • of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US11515245B2 cover?
The present invention relates to a method for manufacturing an insulating layer for a semiconductor package which can improve reliability and have excellent heat resistance by removing pores generated in the insulating layer during manufacture of an insulating layer for a semiconductor package using magnetic characteristics, and an insulating layer for a semiconductor package obtained using the…
Who is the assignee on this patent?
Lg Chemical Ltd
What technology area does this patent fall under?
Primary CPC classification H10W70/69. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Nov 29 2022 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).