Conductive structures for contacting a top electrode of an embedded memory device and methods of making such contact structures on an IC product

Patent metadata

Field	Value
Publication number	US-11515205-B2
Application number	US-201916556465-A
Country	US
Kind code	B2
Filing date	Aug 30, 2019
Priority date	Aug 30, 2019
Publication date	Nov 29, 2022
Grant date	Nov 29, 2022

Abstract

One illustrative method disclosed herein includes forming at least one first layer of insulating material above an upper surface of a top electrode of a memory cell, forming a patterned etch stop layer above the at least one first layer of insulating material, wherein the patterned etch stop layer has an opening that is positioned vertically above at least a portion of the upper surface of the top electrode and forming at least one second layer of insulating material above an upper surface of the etch stop layer. The method also includes forming a conductive contact opening that extends through the etch stop layer to expose at least a portion of the upper surface of the top electrode and forming a conductive contact structure in the conductive contact opening, wherein the conductive contact structure is conductively coupled to the upper surface of the top electrode.

First claim

The invention claimed is:

1. An integrated circuit product, comprising:
a first metallization layer having a first insulating layer, a second insulating layer over the first insulating layer, and an etch stop layer over the first insulating layer separating the first insulating layer from the second insulating layer,
wherein the first insulating layer includes a first material that is substantially uniform throughout the first insulating layer, the second insulating layer includes a second material, and the etch stop layer includes a third material different than the first material and the second material;
a memory cell positioned in the first insulating layer of the first metallization layer, the memory cell comprising an upper electrode having an upper surface that is positioned at a first level within the first metallization layer relative to a reference surface located below the first metallization layer, and a lower electrode that is positioned below the upper electrode within the first metallization layer relative to the reference surface,
wherein the lower electrode is laterally surrounded by the first insulating layer from an upper surface of the lower electrode to a lower surface of the lower electrode,
wherein the lower surface of the lower electrode is substantially coplanar with a lower surface of the first insulating layer;
a conductive line positioned in the first metallization layer, the conductive line comprising a bottom surface that is positioned at a second level within the first metallization layer relative to the reference surface, wherein the first level is above the second level, and the second level is above the lower electrode relative to the reference surface; and
a conductive contact structure that is conductively coupled to the upper surface of the upper electrode,
wherein a portion of the conductive contact structure extends through the first insulating layer, the etch stop layer, and the second insulating layer.

2. The integrated circuit product of claim 1 , wherein the memory cell comprises one of an MTJ (magnetic tunnel junction) memory device, an RRAM (resistive random access memory) device, a PRAM (phase-change random access memory) device, an MRAM (magnetic random access memory) device, or a FRAM (ferroelectric random access memory) device.

3. The integrated circuit product of claim 1 , wherein the integrated circuit product comprises at least one transistor device having a gate length that extends in a gate length direction, wherein the upper electrode has a first lateral width in the gate length direction and wherein the conductive contact structure, at a location where the conductive contact structure physically contacts the upper surface of the upper electrode, has a second lateral width in the gate length direction that is less than the first lateral width,
wherein the conductive contact structure comprises at least one of copper, aluminum, or tungsten, and
wherein the conductive contact structure comprises the conductive line and a conductive via, wherein the conductive via physically contacts the upper surface of the upper electrode.

4. The integrated circuit product of claim 1 , wherein the upper electrode in the memory cell is separated from the etch stop layer.

5. The integrated circuit product of claim 1 , wherein the third material of the etch stop layer comprises at least one of: silicon nitride, carbon-doped nitride (NDC), aluminum, or oxygen-doped silicon carbide (ODC), and wherein the first material of the first insulating layer and the second material of the second insulating layer comprise at least one of: silicon dioxide or a low-k material.

6. The integrated circuit product of claim 1 , wherein the etch stop layer has a substantially uniform vertical thickness.

7. The integrated circuit product of claim 1 , further comprising a second conductive contact structure that is conductively coupled to the lower surface of the lower electrode.

8. The integrated circuit product of claim 7 , wherein the second conductive contact structure includes a conductive via physically contacting the lower surface of the lower electrode.

9. An integrated circuit product, comprising:
a first metallization layer;
a memory cell positioned in the first metallization layer, the memory cell comprising an upper electrode having an upper surface that is positioned at a first level within the first metallization layer relative to a reference surface located below the first metallization layer, and a lower electrode that is positioned below the upper electrode within the first metallization layer relative to the reference surface;
a conductive line positioned in the first metallization layer, the conductive line comprising a bottom surface that is positioned at a second level within the first metallization layer relative to the reference surface, wherein the first level is above the second level, and the second level is above the lower electrode relative to the reference surface; and
a conductive contact structure that is conductively coupled to the upper surface of the upper electrode,
wherein the first metallization layer comprises a first insulating material layer positioned above the first level, an etch stop layer positioned above the first insulating material layer, and a second insulating material layer positioned over the etch stop layer, wherein a portion of the conductive contact structure extends through the first insulating material layer, the etch stop layer and the second insulating material layer,
wherein the first insulating material layer includes a first material that is substantially uniform throughout the first insulating layer,
wherein the conductive contact structure comprises the conductive line and a conductive via, wherein the conductive via physically contacts the upper surface of the upper electrode, and wherein the upper surface of the upper electrode is separated from the etch stop layer,
wherein the lower electrode is laterally surrounded by the first insulating layer from an upper surface of the lower electrode to a lower surface of the lower electrode,
wherein the lower surface of the lower electrode is substantially coplanar with a lower surface of the first insulating layer.

10. The integrated circuit product of claim 9 , wherein the memory cell comprises one of: an RRAM (resistive random access memory) device, a PRAM (phase-change random access memory) device, an MRAM (magnetic random access memory) device, or a FRAM (ferroelectric random access memory) device.

11. The integrated circuit product of claim 9 , wherein the upper surface of the upper electrode is positioned at the first level above the second level, wherein the bottom surface of the conductive line is positioned at the second level, and wherein the conductive line is a nearest conductive line to the memory cell within the first metallization layer.

12. The integrated circuit product of claim 11 , wherein the first level and the second level are vertically spaced by up to 15 nanometers (nm).

13. The integrated circuit product of claim 9 , wherein the conductive line is a nearest conductive line to the memory cell within the first metallization layer.

14. The integrated circuit product of claim 13 , wherein the conductive contact structure comprises at least one of copper, aluminum, or tungsten.

15. The integrated circuit product of claim 13 , wherein the etch stop layer comprises at least one of: silicon nitride, carbon-doped nitride (NDC), aluminum, or oxygen-doped silicon carbide (ODC), and wherein the insulating material comprises at least one of: silicon dioxide or a low-k material,

Assignees

• Globalfoundries Us Inc

Inventors

• Ramanathan Eswar
• Singh Sunil Kumar
• Tran Xuan Anh
• Kalaga Suryanarayana
• Tan Juan Boon

Classifications

• H10W20/0693

  by forming self-aligned vias · CPC title

• H10W20/0696

  by using sacrificial placeholders, e.g. using sacrificial plugs · CPC title

• H10W20/069 Primary

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H01L21/76897 Primary

  Electricity · mapped topic

• H01L43/12

  Electricity · mapped topic