Managing collisions in a non-volatile memory system with a coherency checker

Patent metadata

Field	Value
Publication number	US-11513959-B2
Application number	US-202117185059-A
Country	US
Kind code	B2
Filing date	Feb 25, 2021
Priority date	Jun 7, 2019
Publication date	Nov 29, 2022
Grant date	Nov 29, 2022

Abstract

A request to read data from a location associated with a memory component is received. The request is assigned a first tag, the first tag having a first identifier of a first buffer to store data read from the location. The request to read data is determined to collide with an earlier request to write data to the location. The earlier request is assigned a second tag, the second tag having a second identifier of a second buffer to store data to write to the location. An attempt to lock the second tag and the second buffer for the request to read data is made. The request to read data is fulfilled from the second buffer in response to a successful attempt to lock the second tag and the second buffer.

First claim

What is claimed is:

1. A method comprising:
receiving a current request to write data to an address of a memory component, the current request assigned a buffer to store the data, a first tag based on the address, and an identifier entry identifying metadata for the current request to write data to the address;
determining that the current request to write data collides with an earlier request to write data to the address based on the earlier request being assigned a second tag that matches the first tag; and
overwriting an identifier entry identifying metadata for the earlier request to write data to the address with the identifier entry identifying metadata for the current request to write data to the address in response to determining the current request collides with the earlier request.

2. The method of claim 1 , further comprising:
determining that the current request to write data originated from a host device.

3. The method of claim 1 , further comprising:
allocating and filling a write buffer with data identified by the current request to write data.

4. The method of claim 1 , wherein determining that the request to write data collides with the earlier request is based on a match of a hash of the address to an entry in a row or an extension of the row of an N-way associative cache structure.

5. The method of claim 4 , wherein the row is identified based on the address and a number of rows in the cache structure.

6. The method of claim 4 , wherein the extension of the row and the first tag are of the same size of data.

7. The method of claim 1 ,
wherein the identifier entry identifying metadata for the current request to write data to the address includes information identifying one or more buffers for storing the write data of the current request to write data; and
wherein the identifier entry identifying metadata for the earlier request to write data to the address includes information identifying one or more buffers for storing the write data of the earlier request to write data.

8. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to:
receive a current request to write data to an address of a memory component, the current request assigned a buffer to store the data, a first tag based on the address, and an identifier entry identifying metadata for the current request to write data to the address;
determine that the current request to write data collides with an earlier request to write data to the address based on the earlier request being assigned a second tag that matches the first tag; and
overwrite an identifier entry identifying metadata for the earlier request to write data to the address with the identifier entry identifying metadata for the current request to write data to the address in response to determining the current request collides with the earlier request.

9. The non-transitory computer-readable medium of claim 8 , wherein the processing device is further to:
determine that the current request to write data originated from a host device.

10. The non-transitory computer-readable medium of claim 8 , wherein the processing device is further to:
allocate and fill a write buffer with data identified by the current request to write data.

11. The non-transitory computer-readable medium of claim 8 , wherein determining that the request to write data collides with the earlier request is based on a match of a hash of the address to an entry in a row or an extension of the row of an N-way associative cache structure.

12. The non-transitory computer-readable medium of claim 11 , wherein the row is identified based on the address and a number of rows in the cache structure.

13. The non-transitory computer-readable medium of claim 11 , wherein the extension of the row and the first tag are of the same size of data.

14. The non-transitory computer-readable medium of claim 8 ,
wherein the identifier entry identifying metadata for the current request to write data to the address includes information identifying one or more buffers for storing the write data of the current request to write data; and
wherein the identifier entry identifying metadata for the earlier request to write data to the address includes information identifying one or more buffers for storing the write data of the earlier request to write data.

15. A system comprising:
a memory device; and
a processing device, operatively coupled with the memory device, to:
receive a current request to write data to an address of a memory component, the current request assigned a buffer to store the data, a first tag based on the address, and an identifier entry identifying metadata for the current request to write data to the address;
determine that the current request to write data originated from a host device and that the current request to write data collides with an earlier request to write data to the address based on the earlier request being assigned a second tag that matches the first tag; and
overwrite an identifier entry identifying metadata for the earlier request to write data to the address with the identifier entry identifying metadata for the current request to write data to the address in response to determining the current request collides with the earlier request.

16. The system of claim 15 , wherein the processing device is further to:
allocate and fill a write buffer with data identified by the current request to write data.

17. The system of claim 15 , wherein determining that the request to write data collides with the earlier request is based on a match of a hash of the address to an entry in a row or an extension of the row of an N-way associative cache structure.

18. The system of claim 17 , wherein the row is identified based on the address and a number of rows in the cache structure.

19. The system of claim 17 , wherein the extension of the row and the first tag are of the same size of data.

20. The system of claim 15 ,
wherein the identifier entry identifying metadata for the current request to write data to the address includes information identifying one or more buffers for storing the write data of the current request to write data; and
wherein the identifier entry identifying metadata for the earlier request to write data to the address includes information identifying one or more buffers for storing the write data of the earlier request to write data.

Assignees

• Micron Technology Inc

Inventors

• Simionescu Horia C
• Adams Lyle E
• Xu Yongcai
• Ish Mark

Classifications

• G06F3/0656

  Data buffering arrangements · CPC title

• G06F12/0857 Primary

  by multiple requestors · CPC title

• G06F2212/1016

  Performance improvement · CPC title

• G06F13/1673

  using buffers · CPC title

• G11C16/3422 Primary

  Circuits or methods to evaluate read or write disturbance in nonvolatile memory, without steps to mitigate the problem · CPC title