Concurrent compute and ECC for in-memory matrix vector operations

Patent metadata

Field	Value
Publication number	US-11513893-B2
Application number	US-202017128414-A
Country	US
Kind code	B2
Filing date	Dec 21, 2020
Priority date	Dec 21, 2020
Publication date	Nov 29, 2022
Grant date	Nov 29, 2022

Abstract

A system includes a compute circuit that preemptively performs a computation on a data word before receiving an indication of data errors from an error checking and correction (ECC) circuit. The ECC circuit reads the data word from a memory array and performs error detection and error correction on the data word. The compute circuit reads the data word and performs the computation on the data word to generate an output value, without waiting for the ECC circuit to check and correct the data word. In response to error detection in the data word by the ECC circuit, the compute circuit delays outputting the output value until correction of the output value in accordance with the error detection by the ECC circuit.

First claim

What is claimed is:

1. An apparatus comprising:
a memory array to store a data word;
an error checking and correction (ECC) circuit to read the data word and perform error detection on the data word and generate an error signal capable to indicate whether an error was detected in the data word; and
a compute circuit to read the data word and begin a computation on the data word prior to generation of the error signal, wherein the computation is to generate an output value;
wherein in response to the error detection in the data word indicated by the error signal generated by the ECC circuit, the output value is delayed until correction of the output value in accordance with the error detection by the ECC circuit.

2. The apparatus of claim 1 , wherein the ECC circuit comprises an error detection circuit and an error correction circuit separate from the error detection circuit.

3. The apparatus of claim 2 , wherein the compute circuit comprises a first compute circuit to generate a first output value, and further comprising a second compute circuit to generate a second output value;
wherein the first compute circuit has a first error detection circuit and the second compute circuit has a second error detection circuit, wherein the first compute circuit and the second compute circuit share the error correction circuit.

4. The apparatus of claim 3 , wherein the memory array comprise a first memory array to store a first data word, the first compute circuit to generate the first output value from the first data word, and further comprising a second memory array to store a second data word, the second compute circuit to generate the second output value from the second data word.

5. The apparatus of claim 1 , wherein the ECC circuit is to correct the output value.

6. The apparatus of claim 1 , further comprising a data path with circuitry to correct the output value.

7. The apparatus of claim 1 , wherein the ECC circuit is to perform the error detection on the data word in one operation cycle, and wherein the compute circuit is to perform the computation on the data word in one operation cycle.

8. The apparatus of claim 1 , wherein the compute circuit comprises a compute near memory (CNM) circuit.

9. The apparatus of claim 8 , wherein the CNM circuit comprises a multiply-accumulate (MAC) circuit.

10. The apparatus of claim 1 , wherein the memory array comprises an array of static random access memory (SRAM) cells.

11. The apparatus of claim 1 , wherein the memory array comprises an array of dynamic random access memory (DRAM) cells.

12. The apparatus of claim 1 , wherein the memory array comprises an array of resistive-based random access memory (RAM) cells.

13. A computing device, comprising:
a host processor; and
an accelerator circuit including
a memory array to store a data word;
an error checking and correction (ECC) circuit to read the data word and perform error detection on the data word and generate an error signal capable to indicate whether an error was detected in the data word; and
a compute circuit to read the data word and begin a computation on the data word prior to generation of the error signal, wherein the computation is to generate an output value;
wherein in response to the error detection in the data word indicated by the error signal generated by the ECC circuit, outputting of the output value is delayed until correction of the output value in accordance with the error detection by the ECC circuit.

14. The computing device of claim 13 , wherein the ECC circuit comprises an error detection circuit and an error correction circuit separate from the error detection circuit.

15. The computing device of claim 14 , wherein the compute circuit comprises a first compute circuit to generate a first output value, and further comprising a second compute circuit to generate a second output value;
wherein the first compute circuit has a first error detection circuit and the second compute circuit has a second error detection circuit, wherein the first compute circuit and the second compute circuit share the error correction circuit.

16. The computing device of claim 15 , wherein the memory array comprise a first memory array to store a first data word, the first compute circuit to generate the first output value from the first data word, and further comprising a second memory array to store a second data word, the second compute circuit to generate the second output value from the second data word.

17. The computing device of claim 13 , wherein the ECC circuit is to correct the output value.

18. The computing device of claim 13 , the accelerator circuit further including a data path with circuitry to correct the output value.

19. The computing device of claim 13 , wherein the compute circuit comprises a compute near memory (CNM) circuit.

20. The computing device of claim 13 , wherein the host processor comprises a multicore central processing unit (CPU) or a multicore graphics processing unit (GPU).

21. The computing device of claim 20 , further comprising:
a display communicatively coupled to the host processor;
a network interface communicatively coupled to the host processor; or
a battery to power the computing device.

Assignees

• Intel Corp

Inventors

• Paul Somnath
• Augustine Charles
• Koren Chen
• Shchupak George
• Khellah Muhammad M

Classifications

• G11C29/42 Primary

  using error correcting codes [ECC] or parity check · CPC title

• G06N3/063

  using electronic means · CPC title

• G11C29/26

  Accessing multiple arrays (G11C29/24 takes precedence) · CPC title

• G06F11/1048 Primary

  using arrangements adapted for a specific error detection or correction feature · CPC title

• G06F11/1068 Primary

  in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence) · CPC title