Compute-in-memory bit cell

Patent metadata

Field	Value
Publication number	US-10964356-B2
Application number	US-201916706429-A
Country	US
Kind code	B2
Filing date	Dec 6, 2019
Priority date	Jul 3, 2019
Publication date	Mar 30, 2021
Grant date	Mar 30, 2021

Abstract

A charge sharing Compute In Memory (CIM) may comprise an XNOR bit cell with an internal capacitor between the XNOR output node and a system voltage. Alternatively, a charge sharing CIM may comprise an XNOR bit cell with an internal capacitor between the XNOR output node and a read bit line. Alternatively, a charge sharing CIM may comprise an XNOR bit cell with an internal cap between XNOR and read bit line with a separate write bit line and write bit line bar.

First claim

What is claimed is:

1. A bit cell circuit comprising:
a bit cell coupled to a system voltage and a ground;
a first signal line coupled to the bit cell;
a second signal line coupled to the bit cell;
a third signal line coupled to the bit cell;
a fourth signal line coupled to the bit cell;
a read transistor coupled to a first read signal line, an output of the bit cell, and a first read bit line; and
a capacitor directly coupled to the bit cell output and the ground.

2. The bit cell circuit of claim 1 , wherein the bit cell comprises a first transistor coupled to the first signal line, a second transistor coupled to the second signal line, a third transistor coupled to the third signal line, and a fourth transistor coupled to the fourth signal line.

3. The bit cell circuit of claim 2 , wherein the bit cell comprises four transistors configured as a first inverter and a second inverter to perform a latch function on a data bit.

4. The bit cell circuit of claim 2 , wherein the first transistor is a P type transistor, the second transistor is a P type transistor, the third transistor is an N type transistor, and a fourth transistor is an N type transistor.

5. The bit cell circuit of claim 1 , wherein the read transistor is an N type transistor.

6. The bit cell circuit of claim 1 , wherein the bit cell circuit is configured to perform a XNOR operation on the first signal line, the second signal line, the third signal line, and the fourth signal line.

7. The bit cell circuit of claim 1 , wherein the bit cell circuit is a charge sharing static random access memory in a compute in memory array of a neural network.

8. The bit cell circuit of claim 1 , wherein the capacitor provides a path to ground to prevent the output from floating.

9. The bit cell circuit of claim 1 , wherein the bit cell circuit is incorporated into a device selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, and a device in an automotive vehicle.

10. A bit cell circuit comprising:
a bit cell coupled to a system voltage and a ground;
a first signal line coupled to the bit cell;
a second signal line coupled to the bit cell;
a third signal line coupled to the bit cell;
a fourth signal line coupled to the bit cell;
a read transistor coupled to a first read signal line, an output of the bit cell, and the ground; and
a capacitor coupled to the bit cell output and the read bit line.

11. The bit cell circuit of claim 10 , wherein the bit cell comprises a first transistor coupled to the first signal line, a second transistor coupled to the second signal line, a third transistor coupled to the third signal line, and a fourth transistor coupled to the fourth signal line.

12. The bit cell circuit of claim 11 , wherein the bit cell comprises four transistors configured as a first inverter and a second inverter to perform a latch function on a data bit.

13. The bit cell circuit of claim 11 , wherein the first transistor is a P type transistor, the second transistor is a P type transistor, the third transistor is an N type transistor, and a fourth transistor is an N type transistor.

14. The bit cell circuit of claim 10 , wherein the read transistor is an N type transistor.

15. The bit cell circuit of claim 10 , wherein the bit cell circuit is configured to perform a XNOR operation on the first signal line, the second signal line, the third signal line, and the fourth signal line.

16. The bit cell circuit of claim 10 , wherein the bit cell circuit is a charge sharing static random access memory in a compute in memory array of a neural network.

17. The bit cell circuit of claim 10 , wherein the capacitor provides a path to ground to prevent the output from floating.

18. The bit cell circuit of claim 10 , wherein the bit cell circuit is incorporated into a device selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, and a device in an automotive vehicle.

19. A bit cell circuit comprising:
a bit cell coupled to a system voltage and a ground;
a first signal line coupled to the bit cell;
a second signal line coupled to the bit cell;
a third signal line coupled to the bit cell;
a fourth signal line coupled to the bit cell;
a read transistor coupled to a first read signal line, an output of the bit cell, and a write bit line bar;
a write bit line coupled to third signal line and the fourth signal line; and
a capacitor coupled to the bit cell output and the read bit line.

20. The bit cell circuit of claim 19 , wherein the bit cell comprises a first transistor coupled to the first signal line, a second transistor coupled to the second signal line, a third transistor coupled to the third signal line, and a fourth transistor coupled to the fourth signal line.

21. The bit cell circuit of claim 20 , wherein the bit cell comprises four transistors configured as a first inverter and a second inverter to perform a latch function on a data bit.

22. The bit cell circuit of claim 20 , wherein the first transistor is a P type transistor, the second transistor is a P type transistor, the third transistor is an N type transistor, and a fourth transistor is an N type transistor.

23. The bit cell circuit of claim 19 , wherein the read transistor is an N type transistor.

24. The bit cell circuit of claim 19 , wherein the bit cell circuit is configured to perform a XNOR operation on the first signal line, the second signal line, the third signal line, and the fourth signal line.

25. The bit cell circuit of claim 19 , wherein the bit cell circuit is a charge sharing static random access memory in a compute in memory array of a neural network.

26. The bit cell circuit of claim 19 , wherein the capacitor provides a path to ground to prevent the output from floating.

27. The bit cell circuit of claim 19 , wherein the bit cell circuit is incorporated into a device selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, and a device in an automotive vehicle.

28. A method for operating a bit cell circuit, the method comprising:
resetting the bit cell circuit to an initial state;
applying a first voltage signal to a first signal line;
applying a second voltage signal to a second signal line;
coupling a first read bit line to an output of the bit cell circuit; and
sampling a voltage level of the first read bit line.

29. The method of claim 28 , wherein the resetting the bit circuit to the initial state comprises coupling the first read bit line to a ground and coupling a first read signal line to a system voltage.

30. The method of claim 29 , wherein the first voltage signal and the

Assignees

• Qualcomm Inc

Inventors

• Wang Zhongze
• Li Xia
• Lu Ye
• Gao Yandong

Classifications

• G06N3/065

  Analogue means · CPC title

• G06N3/048

  Activation functions · CPC title

• G11C11/412 Primary

  using field-effect transistors only · CPC title

• G11C8/14

  Word line organisation; Word line lay-out · CPC title

• G11C7/12

  Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines · CPC title