Image sensor semiconductor packages and related methods

Patent metadata

Field	Value
Publication number	US-11508776-B2
Application number	US-201916374720-A
Country	US
Kind code	B2
Filing date	Apr 3, 2019
Priority date	May 31, 2016
Publication date	Nov 22, 2022
Grant date	Nov 22, 2022

Abstract

An image sensor semiconductor package (package) includes a printed circuit board (PCB) having a first surface and a second surface opposite the first surface. A complementary metal-oxide semiconductor (CMOS) image sensor (CIS) die has a first surface with a photosensitive region and a second surface opposite the first surface of the CIS die. The second surface of the CIS die is coupled with the first surface of the PCB. A transparent cover is coupled over the photosensitive region of the CIS die. An image signal processor (ISP) is embedded within the PCB. One or more electrical couplers electrically couple the CIS die with the PCB. A plurality of electrical contacts on the second surface of the PCB are electrically coupled with the CIS die and with the ISP. The ISP is located between the plurality of electrical contacts of the second surface of the PCB and the CIS die.

First claim

What is claimed is:

1. An image sensor semiconductor package, comprising:
a printed circuit board (PCB) comprising a first surface and a second surface opposite the first surface;
an interposer comprising a first surface and a second surface opposite the first surface of the interposer, the interposer comprising a recess in its second surface extending only partially through the interposer;
a complementary metal-oxide semiconductor (CMOS) image sensor (CIS) die comprising a first surface comprising a photosensitive region and a second surface opposite the first surface of the CIS die, the second surface of the CIS die coupled with the first surface of the interposer; and
an image signal processor (ISP) coupled within the recess of the interposer.

2. The package of claim 1 , wherein the interposer further comprises one or more electrical vias passing through the interposer from the first surface of the interposer to the second surface of the interposer.

3. The package of claim 1 , further comprising one or more electrical couplers electrically coupling the CIS die with the PCB through one or more electrical vias of the interposer.

4. The package of claim 1 , further comprising a plurality of electrical contacts comprised at the second surface of the PCB and electrically coupled with the CIS die and with the ISP.

5. The package of claim 4 , wherein the plurality of electrical contacts comprised at the second surface of the PCB comprise solder bumps.

6. The package of claim 4 , wherein the plurality of electrical contacts comprise one of aluminum, gold plating, copper plating, a copper pillar bump, and a gold stud.

7. The package of claim 1 , further comprising one or more redistribution layers (RDLs) fanning out one or more electrical contacts of the ISP by electrically coupling the one or more electrical contacts of the ISP with one or more of a plurality of electrical contacts comprised at the second surface of the PCB.

8. The package of claim 1 , wherein the ISP is mechanically coupled with the recess through one of an adhesive or a tape.

9. An image sensor semiconductor package, comprising:
a printed circuit board (PCB) comprising a first surface and a second surface opposite the first surface;
an interposer comprising a first surface and a second surface opposite the first surface of the interposer, the interposer comprising a recess in its second surface and comprising one or more electrical vias passing through the interposer from the first surface of the interposer to the second surface of the interposer, wherein the recess extends only partially through the interposer;
a complementary metal-oxide semiconductor (CMOS) image sensor (CIS) die comprising a first surface comprising a photosensitive region and a second surface opposite the first surface of the CIS die, the second surface of the CIS die coupled with the first surface of the interposer;
an image signal processor (ISP) coupled within the recess of the interposer; and
one or more electrical couplers electrically coupling the CIS die with the PCB through the one or more electrical vias of the interposer.

10. The package of claim 9 , further comprising a plurality of electrical contacts comprised at the second surface of the PCB and electrically coupled with the CIS die and with the ISP.

11. The package of claim 10 , wherein the plurality of electrical contacts comprised at the second surface of the PCB comprise solder bumps.

12. The package of claim 10 , wherein the plurality of electrical contacts comprise one of aluminum, gold plating, copper plating, a copper pillar bump, and a gold stud.

13. The package of claim 9 , further comprising one or more redistribution layers (RDLs) fanning out one or more electrical contacts of the ISP by electrically coupling the one or more electrical contacts of the ISP with one or more of a plurality of electrical contacts comprised at the second surface of the PCB.

14. The package of claim 9 , wherein the ISP is mechanically coupled with the recess through one of an adhesive or a tape.

15. The package of claim 9 , wherein the package does not comprise an image signal processor at the second surface of the PCB.

16. A method of forming an image sensor semiconductor package, comprising:
providing an interposer comprising a first surface and a second surface opposite the first surface of the interposer, the second surface of the interposer comprising a recess therein extending only partially through the interposer;
forming one or more electrical vias through the interposer from the first surface of the interposer to the second surface of the interposer;
coupling an image signal processor (ISP) within the recess of the interposer and electrically coupling the ISP with the one or more electrical vias;
coupling the interposer with a first surface of a printed circuit board (PCB), the PCB also having a second surface opposite the first surface of the PCB;
coupling a complementary metal-oxide semiconductor (CMOS) image sensor (CIS) die with the interposer, the CIS die comprising a first surface comprising a photosensitive region and a second surface opposite the first surface of the CIS die, the second surface of the CIS die coupled with the first surface of the interposer;
electrically coupling the CIS die with one or more electrical contacts located at the second surface of the PCB through the one or more electrical vias of the interposer; and
electrically coupling the ISP with the CIS die through the one or more electrical vias of the interposer.

17. The method of claim 16 , wherein the recess in the interposer is formed through a wet-etching wafer level process.

18. The method of claim 16 , wherein the one or more electrical vias are formed through one of drilling and etching.

19. The method of claim 16 , further comprising at least partially encapsulating the CIS die in an encapsulant.

20. The method of claim 16 , further comprising forming one or more redistribution layers (RDLs) electrically coupling one or more electrical contacts of the ISP with one or more of a plurality of electrical contacts comprised at the second surface of the PCB.

Assignees

• Semiconductor Components Ind Llc

Inventors

• Kinsman Larry
• Lin Yusheng
• Hsieh Yu-Te
• Skeete Oswald
• Wu Weng-Jin
• Kuo Chi-Yao

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W74/016

  using moulds · CPC title