Semiconductor devices having 3-dimensional inductive structures

Patent metadata

Field	Value
Publication number	US-11508657-B2
Application number	US-202016990886-A
Country	US
Kind code	B2
Filing date	Aug 11, 2020
Priority date	Nov 7, 2018
Publication date	Nov 22, 2022
Grant date	Nov 22, 2022

Abstract

Semiconductor devices having inductive structures, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a substrate and at least one circuit component coupled to the substrate. The semiconductor device can further include an inductive structure carried by the substrate and having a stack of alternating first and second layers. In some embodiments, the first layers comprise an oxide material and the second layers each include a coil of conductive material. The coils of conductive material can be electrically coupled (a) together to form an inductor and (b) to the at least one circuit component.

First claim

We claim:

1. An inductive structure, comprising:
a plurality of layers of electrically insulative material arranged in a stack, wherein the layers are at least partially offset from one another to define a stepped portion of the stack, and wherein each of the layers includes a peripheral region that is exposed from the stack at the stepped portion;
a plurality of loops of electrically conductive material formed in corresponding ones of the layers; and
a metallization structure over the stack and electrically coupling the loops together.

2. The inductive structure of claim 1 wherein the loops are electrically accessible at the stepped portion.

3. The inductive structure of claim 2 , further comprising a plurality of conductive columns extending between the stepped portion of the stack and the metallization structure, wherein the conductive columns electrically couple the metallization structure to the loops.

4. The inductive structure of claim 1 , further comprising an oxide material over the stepped portion of the stack.

5. The inductive structure of claim 4 wherein the oxide material is further over an uppermost layer of the plurality of layers.

6. The inductive structure of claim 1 wherein the loops are electrically coupled together in series.

7. The inductive structure of claim 1 wherein individual ones of the loops include a first end portion and a second end portion, wherein the first and second end portions are positioned at the stepped portion of the stack.

8. The inductive structure of claim 7 , further comprising a plurality of conductive columns, wherein individual ones of the conductive columns are connected to the first end portion of a corresponding one of the loops or the second end portion of a corresponding one of the loops.

9. The inductive structure of claim 1 wherein the electrically insulative material of each of the layers comprises a first insulative material over a second insulative material.

10. The inductive structure of claim 9 wherein the first insulative material comprises an oxide material, wherein the second insulative material comprises a nitride material, and wherein the electrically conductive material of the loops comprises tungsten.

11. An inductive structure, comprising:
a substrate;
a stack of tiers carried by the substrate, wherein individual ones of the tiers include a first layer including an insulative material and a second layer including a loop of conductive material, wherein the stack includes a staircase portion at which a peripheral region of each of the tiers is exposed from the stack, wherein a portion of each of the loops of conductive material is exposed at the peripheral region, wherein the insulative material is an oxide material, wherein the conductive material is tungsten, and wherein the second layers further include a nitride material at least partially around the tungsten; and
a metallization structure carried by the substrate, wherein the loops of conductive material are electrically coupled to the metallization structure.

12. The inductive structure of claim 11 wherein the metallization structure electrically couples the loops together such that they form an inductor.

13. The inductive structure of claim 12 wherein the metallization structure electrically couples the inductor to a 3D-NAND memory array.

14. The inductive structure of claim 13 wherein the 3D-NAND memory array is carried by the substrate.

15. The inductive structure of claim 11 wherein the metallization structure electrically couples the loops together in series.

16. The inductive structure of claim 11 , wherein the loops have different radii.

17. The inductive structure of claim 11 , further comprising:
an oxide material over the staircase portion of the stack; and
a plurality of conductive members extending through the oxide material between the metallization structure and corresponding ones of the loops of conductive material.

18. The inductive structure of claim 11 wherein the first and second layers are generally planar.

19. The inductive structure of claim 11 wherein individual ones of the first layers are covered by an adjacent one of the second layers at the staircase portion of the stack.

20. A memory device, comprising:
a substrate;
a 3D-NAND memory array carried by the substrate; and
an inductive structure carried by the substrate, wherein the inductive structure includes—
a plurality of layers of electrically insulative material arranged in a stack, wherein the layers are at least partially offset from one another to define a stepped portion of the stack, and wherein each of the layers includes a peripheral region that is exposed from the stack at the stepped portion;
a plurality of loops of electrically conductive material formed in corresponding ones of the layers; and
a metallization structure over the stack and electrically coupling the loops together, wherein the metallization structure electrically couples the inductor to the 3D-NAND memory array.

Assignees

• Micron Technology Inc

Inventors

• Davis James E
• Duesman Kevin G

Classifications

• H10W44/501

  Inductive arrangements (H10W44/20 takes precedence) · CPC title

• H10W44/20

  at high-frequency [HF] or radio frequency [RF] · CPC title

• H10W42/80

  protecting against overcurrent or overload, e.g. fuses or shunts (integrated devices comprising arrangements for electrical protection H10D89/60) · CPC title

• H10W20/4441

  the principal metal being a refractory metal · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title