Semiconductor package having routable encapsulated conductive substrate and method

Patent metadata

Field	Value
Publication number	US-11508635-B2
Application number	US-202016861405-A
Country	US
Kind code	B2
Filing date	Apr 29, 2020
Priority date	Sep 8, 2015
Publication date	Nov 22, 2022
Grant date	Nov 22, 2022

Abstract

A packaged semiconductor device includes a routable molded lead frame structure with a surface finish layer. In one embodiment, the routable molded lead frame structure includes a first laminated layer including the surface finish layer, vias connected to the surface finish layer, and a first resin layer covering the vias leaving the top surface of the surface finish layer exposed. A second laminated layer includes second conductive patterns connected to the vias, bump pads connected to the second conductive patterns, and a second resin layer covering one side of the first resin layer, the second conductive patterns and the bump pads. A semiconductor die is electrically connected to the surface finish layer and an encapsulant covers the semiconductor die and another side of the first resin layer. The surface finish layer provides a customizable and improved bonding structure for connecting the semiconductor die to the routable molded lead frame structure.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, comprising:
providing a routable encapsulated conductive substrate comprising:
a first conductive structure encapsulated within a first laminated layer, wherein the first laminated layer has a first thickness and the first conductive structure is entirely within the first thickness;
a second conductive structure encapsulated within a second laminated layer, wherein the second laminated layer has a second thickness and the second conductive structure is entirely within the second thickness; and
a first surface finish layer disposed on at least portions of the first conductive structure, wherein:
the first laminated layer and the second laminated layer form an interface;
the first conductive structure and the second conductive structure meet at the interface;
the first surface finish layer is exposed from the first laminated layer;
first at least portions of the second conductive structure are exposed in the second laminated layer and recessed inward from a bottom side of the second laminated layer; and
second portions of the second conductive structure are substantially co-planar with the interface; and
conductive bumps attached to the first portions of the second conductive structure;
electrically coupling a semiconductor component to the first surface finish layer; and
forming a package body covering the semiconductor component and the first surface finish layer;
wherein providing the routable encapsulated conductive substrate comprises in the following order:
first, providing the first surface finish layer on a carrier;
second, providing the first conductive structure comprising first conductive patterns on both the first surface finish layer and on the carrier where the carrier is devoid of the first surface finish layer and conductive vias on at least portions of the first conductive patterns;
third, providing the first laminated layer covering the carrier, the first surface finish layer, the first conductive patterns, and the conductive vias so that the first surface finish layer, the first conductive patterns, and the conductive vias are entirely within the first thickness;
fourth, providing the second conductive structure comprising second conductive patterns and conductive pads connected to the conductive vias;
fifth, providing the second laminated layer covering the first laminated layer, the second conductive patterns and the conductive pads;
subsequently, (a) and (b) in either order:
(a):
(a1) recessing the first portions of the conductive pads inward from the bottom side of the second laminated layer; and
(a2) attaching the conductive bumps directly to the recessed conductive pads; and

(b) removing the carrier to expose the first surface finish layer.

2. The method of claim 1 , wherein:
the second providing includes removing a portion of the first laminated layer to expose the conductive vias from the first laminated layer before the fourth providing;
the first providing comprises providing the first surface finish layer comprising one or more of nickel/gold (Ni/Au), silver (Ag) or copper (Cu); and
the method further comprises after removing the carrier, recessing surfaces of at least portions of the first conductive patterns below a major surface of the first laminated layer while leaving the first surface finish layer substantially coplanar with the major surface of the first laminated layer.

3. The method of claim 1 further comprising:
removing a portion of the second laminated layer to expose the conductive pads from the second laminated layer; and
forming a second surface finish layer connected to the conductive pads, wherein:
the second surface finish layer comprise one or more of nickel/gold (Ni/Au), silver (Ag) or tin (Sn); and
the second surface finish layer is substantially coplanar with a major surface of the second laminated layer.

4. The method of claim 1 , wherein:
electrically coupling the semiconductor component comprises coupling with conductive bumps in a flip-chip configuration.

5. A method of manufacturing a semiconductor device, comprising:
providing a routable encapsulated conductive substrate comprising:
a first conductive structure encapsulated within a first laminated layer, wherein:
the first conductive structure comprises:
a first surface finish layer;
a first conductive pattern; and
first conductive vias coupled to at least a portion of the first surface conductive pattern;

the first laminated layer defines a top substrate surface of the routable encapsulated conductive substrate and has a first thickness;
the first conductive structure is entirely within the first thickness of the first laminated layer; and
the first surface finish structure is exposed from the top substrate surface;

a second conductive structure electrically coupled to the first conductive vias and encapsulated within a second laminated layer, wherein:
the second conductive structure comprises:
a second conductive pattern; and
conductive pads connected to the second conductive pattern; and

the second laminated layer defines a bottom substrate surface of the routable encapsulated conductive substrate;
the second laminated layer covers a portion of the first laminated layer; and
lower surfaces of the conductive pads proximate to the bottom substrate surface are devoid of the second laminated layer;

electrically coupling a semiconductor device to the first surface finish structure; and
providing a package body covering the semiconductor device, at least portions of the first surface finish layer, and at least portions of the top substrate surface;
wherein providing the routable encapsulated conductive substrate comprises in the following order;
first, providing the first surface finish layer on a carrier;
second, providing the first conductive pattern having a first portion directly on the carrier and a second portion on the first surface finish layer;
third, providing the first conductive vias on at least portions of the first conductive pattern;
fourth, providing the first laminated layer covering the carrier, the first surface finish layer, the first conductive pattern, and the first conductive vias so that the first surface finish layer, the first conductive pattern, and the first conductive vias are entirely within the first thickness;
fifth, providing the second conductive pattern on the conductive vias;
sixth, providing the conductive pads connected to at least a portion of the second conductive pattern;
seventh, providing the second laminated layer covering the first laminated layer, the second conductive pattern and the conductive pads; and
subsequently, removing the carrier.

6. The method of claim 5 , wherein:
the first providing comprises providing the first surface finish layer comprising a first material; and
the third providing comprises providing first conductive vias comprising a second material that is different than the first material.

7. The method of claim 5 , wherein:
the fourth providing comprises providing the first portion of the first conductive pattern and the first surface finish layer substantially coplanar with the substrate top surface.

8. The method of claim 5 , wherein:
the fourth providing comprises providing the first surface finish layer substantially coplanar with the top substrate surface;
after the seventh providing, providing surfaces of the conductive pads recessed within opening in the second laminated layer; and
then directly attaching conductive bumps to the surfaces of the conductive pads in the recessed openings.

9. The method of claim 5 , wherein:
electrically coupling the semiconductor device comprises el

Assignees

• Amkor Tech Singapore Holding Pte Ltd

Inventors

• Bang Won Bae
• Kim Byong Jin
• Kim Gi Jeong
• Kwon Jae Doo
• Jeon Hyung Il

Classifications

• H10W70/6565

  recessed into the surface of the package substrates, interposers, or redistribution layers · CPC title

• H10W72/5522

  comprising gold [Au] · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title