Non-volatile memory system using strap cells in source line pull down circuits

Patent metadata

Field	Value
Publication number	US-11508442-B2
Application number	US-202017074103-A
Country	US
Kind code	B2
Filing date	Oct 19, 2020
Priority date	Apr 17, 2020
Publication date	Nov 22, 2022
Grant date	Nov 22, 2022

Abstract

The present invention relates to a flash memory device that uses strap cells in a memory array of non-volatile memory cells as source line pull down circuits. In one embodiment, the strap cells are erase gate strap cells. In another embodiment, the strap cells are source line strap cells. In another embodiment, the strap cells are control gate strap cells. In another embodiment, the strap cells are word line strap cells.

First claim

What is claimed is:

1. A memory system comprising:
a memory cell comprising a first bit line terminal and a first source line terminal;
a first bit line coupled to the first bit line terminal;
a strap cell comprising a second bit line terminal, a second source line terminal, a first pull down circuit contact, and a second pull down circuit contact;
a second bit line coupled to the second bit line terminal, the first pull down circuit contact, and the second pull down circuit contact, wherein the first pull down circuit contact is located on one end of the second bit line and the second pull down circuit contact is located on an opposite end of the second bit line;
a source line coupled to the first source line terminal and the second source line terminal; and
a pull down circuit coupled to the first pull down circuit contact and the second pull down circuit contact that selectively couples the second bit line to ground when the memory cell is being read or erased and to a voltage source when the memory cell is being programmed.

2. The system of claim 1 , wherein the memory cell comprises a first word line terminal and the strap cell comprises a second word line terminal.

3. The system of claim 2 , wherein the memory cell comprises a first control gate terminal and the strap cell comprises a second control gate terminal.

4. The system of claim 3 , wherein the memory cell comprises a first erase gate terminal and the strap cell comprises a second erase gate terminal.

5. The system of claim 4 , wherein the strap cell is a source line strap cell, wherein the second source line terminal is connected to a source line contact.

6. The system of claim 4 , wherein the strap cell is a word line strap cell, wherein the second word line terminal is connected to a word line contact.

7. The system of claim 4 , wherein the strap cell is a control gate strap cell, wherein the second control gate terminal is connected to a control gate contact.

8. The system of claim 4 , wherein the strap cell is an erase gate strap cell wherein the second erase gate terminal is connected to an erase gate contact.

9. The system of claim 3 , wherein the strap cell is a source line strap cell, wherein the second source line terminal is connected to a source line contact.

10. The system of claim 3 , wherein the strap cell is a word line strap cell, wherein the second word line terminal is connected to a word line contact.

11. The system of claim 3 , wherein the strap cell is a control gate strap cell, wherein the second control line terminal is connected to a control gate contact.

12. The system of claim 2 , wherein the strap cell is a source line strap cell, wherein the second source line terminal is connected to a source line contact.

13. The system of claim 2 , wherein the strap cell is a word line strap cell, wherein the second word line terminal is connected to a word line contact.

14. The system of claim 1 , wherein the strap cell is a source line strap cell, wherein the second source line terminal is connected to a source line contact.

Assignees

• Silicon Storage Tech Inc

Inventors

• Xing leo
• Wang Chunming
• Liu Xian
• Do Nhan
• Lin Guangming
• Zhu Yaohua

Classifications

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/14 Primary

  Circuits for erasing electrically, e.g. erase voltage switching circuits · CPC title

• G11C16/08 Primary

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C16/0433

  comprising cells containing a single floating gate transistor and one or more separate select transistors · CPC title

• G11C16/0425 Primary

  comprising cells containing a merged floating gate and select transistor · CPC title