Displays with reduced temperature luminance sensitivity

Patent metadata

Field	Value
Publication number	US-11508309-B2
Application number	US-202117317128-A
Country	US
Kind code	B2
Filing date	May 11, 2021
Priority date	Mar 4, 2021
Publication date	Nov 22, 2022
Grant date	Nov 22, 2022

Abstract

A display may include an array of pixels. Each pixel in the array may include a drive transistor, emission transistors, a data loading transistor, a gate voltage setting transistor, an initialization transistor, an anode reset transistor, a storage capacitor, and an optional current boosting capacitor. A data refresh may include a initialization phase, a threshold voltage sampling phase, and a data programming phase. The threshold voltage sampling phase can be substantially longer than the data programming phase to decrease a current sampling level during the threshold voltage sampling phase, which helps reduce the display luminance sensitivity to temperature variations.

First claim

What is claimed is:

1. A display, comprising: gate driver circuitry; and a plurality of pixels coupled to the gate driver circuitry, wherein at least one pixel in the plurality of pixels comprises: a light-emitting diode having an anode terminal; a drive transistor coupled in series with the light-emitting diode, the drive transistor having a gate terminal, a first source-drain terminal, and a second source-drain terminal; a data loading transistor having a first source-drain terminal coupled at the gate terminal of the drive transistor, a second source-drain terminal coupled to a data line, and a gate terminal configured to receive a first scan signal from the gate driver circuitry; and a gate voltage setting transistor having a first source-drain terminal coupled to the gate terminal of the drive transistor, a second source-drain terminal configured to receive a reference voltage, and a gate terminal configured to receive a second scan signal from the gate driver circuitry; an anode reset transistor having a first source-drain terminal coupled to the anode terminal, a second source-drain terminal configured to receive an anode reset voltage, and a gate terminal configured to receive a third scan signal, different than the second scan signal, from the gate driver circuitry; a first emission transistor coupled between a positive power supply line and the first source-drain terminal of the drive transistor; and a second emission transistor coupled between the second source-drain terminal of the drive transistor and the anode terminal, wherein the gate driver circuitry is configured to: during a threshold voltage sampling phase, assert the second scan signal; and during a data programming phase, assert the first scan signal, wherein the data programming phase has a first duration and wherein the threshold voltage sampling phase has a second duration that is greater than the first duration, wherein the at least one pixel in the plurality of pixels further comprises: an initialization transistor having a first source-drain terminal coupled to the second source-drain terminal of the drive transistor, a second source-drain terminal configured to receive an initialization voltage, and a gate terminal configured to receive the third scan signal, wherein the gate driver circuitry is configured to assert the second scan signal and the third scan signal during an initialization phase.

2. The display of claim 1 , wherein the gate driver circuitry is configured to perform the threshold voltage sampling phase before the data programming phase during a refresh operation.

3. The display of claim 1 , wherein the second duration is at least ten times longer than the first duration.

4. The display of claim 1 , wherein the first and second emission transistors have gate terminals configured to receive an emission signal from the gate driver circuitry, and wherein the gate driver circuitry is configured to assert the emission signal during the threshold voltage sampling phase.

5. The display of claim 4 , wherein the drive transistor, the data loading transistor, the gate voltage setting transistor, the anode reset transistor, the initialization transistor, the first emission transistor, and the second emission transistor all comprise semiconducting oxide transistors.

6. The display of claim 4 , wherein the at least one pixel in the plurality of pixels further comprises:
a storage capacitor having a first terminal coupled to the gate terminal of the drive transistor and having a second terminal coupled to the anode terminal.

7. The display of claim 6 , wherein the at least one pixel in the plurality of pixels further comprises:
an additional capacitor having a first terminal coupled to the anode terminal and having a second terminal configured to receive a static voltage.

8. The display of claim 1 , wherein the first emission transistor has a gate terminal configured to receive a first emission signal from the gate driver circuitry, wherein the second emission transistor has a gate terminal configured to receive a second emission signal from the gate driver circuitry, and wherein the gate driver circuitry is configured to: during the threshold voltage sampling phase, assert the first emission signal and deassert the second emission signal.

9. The display of claim 8 , wherein the at least one pixel in the plurality of pixels further comprises:
a storage capacitor having a first terminal coupled to the gate terminal of the drive transistor and having a second terminal coupled to the second source-drain terminal of the drive transistor; and
an additional capacitor having a first terminal coupled to the second source-drain terminal of the drive transistor and having a second terminal configured to receive a static voltage.

10. The display of claim 1 , wherein the at least one pixel in the plurality of pixels further comprises: an initialization transistor having a first source-drain terminal coupled to a source-drain terminal of the first emission transistor, a second source-drain terminal configured to receive an initialization voltage, and a gate terminal configured to receive the third scan signal; a storage capacitor having a first terminal coupled to the gate terminal of the drive transistor and having a second terminal coupled to the source-drain terminal of the first emission transistor; and an additional capacitor having a first terminal coupled to the source-drain terminal of the first emission transistor and having a second terminal configured to receive a static voltage.

11. The display of claim 1 , wherein the at least one pixel in the plurality of pixels further comprises:
a storage capacitor having a first terminal coupled to the gate terminal of the drive transistor and having a second terminal coupled to the second source-drain terminal of the drive transistor; and
an additional capacitor having a first terminal coupled to the second source-drain terminal of the drive transistor and having a second terminal configured to receive a static voltage.

12. A method of operating a display having gate driver circuitry and a plurality of pixels each of which includes at least a light-emitting diode, a drive transistor, a data loading transistor, a gate voltage setting transistor, an anode reset transistor, an initialization transistor, at least one emission transistor, and a storage capacitor, the method comprising:
during an initialization phase, resetting an anode of the light-emitting diode by asserting, with the gate driver circuitry, a third scan signal to activate the anode reset transistor;
during the initialization phase, applying a bias voltage to a source-drain terminal of the drive transistor by asserting, with the gate driver circuitry, the third scan signal to activate the initialization transistor and deasserting, with the gate driver circuitry, an emission control signal to deactivate the at least one emission transistor;
during a threshold voltage sampling phase, sampling a threshold voltage of the drive transistor onto the storage capacitor by asserting, with the gate driver circuitry, a second scan signal to activate the gate voltage setting transistor and the emission control signal to activate the at least one emission transistor; and
during a data programming phase, loading data onto the storage capacitor by asserting, with the gate driver circuitry, a first scan signal to activate the data loading transistor, wherein:
the data programming phase occurs after the threshold voltage sampling phase during a data refresh operation;
the data programming phase has a first duration; and
the threshold voltage sampling phase has a second duration that is longer than the first duration.

Assignees

• Apple Inc

Inventors

• Lin Chin-Wei
• Ono Shinya
• Lee Zino

Classifications

• G09G2300/0861

  with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes · CPC title

• G09G2320/041

  Temperature compensation · CPC title

• G09G2300/0819

  used for counteracting undesired variations, e.g. feedback or autozeroing · CPC title

• G09G3/3266 Primary

  Details of drivers for scan electrodes · CPC title

• G09G2300/0852

  being a dynamic memory with more than one capacitor · CPC title