Network interface device and method

Patent metadata

Field	Value
Publication number	US-11502845-B2
Application number	US-202016921590-A
Country	US
Kind code	B2
Filing date	Jul 6, 2020
Priority date	Sep 29, 2017
Publication date	Nov 15, 2022
Grant date	Nov 15, 2022

Abstract

A network interface device comprises an integrated circuit device comprises at least one processor. A network interface device comprises a memory. The integrated device is configured to execute a function with respect to at least a part of stored data in said memory.

First claim

The invention claimed is:

1. A network interface device comprising:
an integrated circuit device comprising at least one processor;
a memory configured to store computer code instructions comprising operations performable by the at least one processor; and
an interface configured to receive from over a network, an indication of one or more locations in the memory;
wherein said integrated circuit device is configured to:
in response to the indication of the one or more locations, execute a function in dependence upon at least part of the computer code that is stored in the memory at the one or more indicated locations to produce a result; and
cause transmission of a result of the execution of the function over the network,

wherein the one or more locations comprises a region of the memory, and the indication of the one or more locations comprises an indication of a start position of the region of the memory, wherein the region of memory extends from the start position over a block having a block size defined for a message authentication code,
wherein the executing the function comprises calculating the message authentication code.

2. A network interface device as claimed in claim 1 , wherein said information identifying a location comprises index information.

3. A network interface device as claimed in claim 2 , wherein said index information comprises an index range.

4. A network interface device as claimed in claim 1 , wherein the result of the execution of the function comprises an array of values.

5. A network interface device as claimed in claim 1 , wherein the memory stores padding bits in addition to the computer code.

6. A network interface device as claimed in claim 1 , wherein said memory comprises at least one of a first memory in said integrated circuit device and a second memory external to said integrated circuit device, wherein said stored computer code is stored in one or more of said first memory and said second memory.

7. A network interface device as claimed in claim 6 , comprising, in said integrated circuit device, a data store configured to store a first encryption key, said at least one processor is configured to encrypt data to be stored in said second memory using said first encryption key.

8. A network interface device as claimed in claim 1 , wherein said function comprises a hash function calculated over the at least part of the computer code.

9. A network interface device as claimed in claim 1 , wherein the at least part of the computer code comprises firmware.

10. A network interface device as claimed in claim 1 , wherein the interface is configured to receive from over a network, a plurality of indications of one or more locations in memory, wherein said integrated circuit device is configured to:
in response to each of the indications of the one or more locations, execute a function in dependence upon at least part of the computer code that is stored in said memory at the respective one or more indicated locations to produce a result; and
cause transmission of each of the results of the executions of the function over a network.

11. A network interface device as claimed in claim 9 , wherein each of the executions of the function is performed in dependence upon a different module of said computer code.

12. A network interface device as claimed in claim 10 , wherein for each of the executions of the function:
prior to executing the respective function in dependence upon the respective module of said computer code, receiving the respective module of computer code from over the network.

13. A network interface device as claimed in claim 11 , wherein each of at least some of the modules is a component of one of at least one of:
an operation system; or
an application.

14. A network interface device as claimed in claim 1 , wherein the interface configured to, prior to receiving the indication of the one or more locations in memory, receive the at least part of the computer code from over the network.

15. A network interface device as claimed in claim 1 , wherein the function is a one-way function.

16. A network interface device as claimed in claim 1 , wherein said integrated circuit device comprises at least one of an ASIC, an FPGA, an integrated circuit.

17. A network interface device as claimed in claim 1 , wherein the interface is configured to receive a nonce value from over the network,
wherein the integrated circuit device is configured to:
encrypt the nonce value with a private key to produce an encrypted nonce; and
cause the encrypted nonce to be transmitted over the network to a same recipient to which the result of the execution of the function is sent.

18. A method comprising: storing in memory, computer code instructions comprising operations performable by the at least one processor; receiving from over a network, an indication of one or more locations in the memory; in response to the indication of the one or more locations, execute a function in dependence upon at least part of the computer code that is stored in the memory at the one or more indicated locations to produce a result; and cause transmission of a result of the execution of the function over a network,
wherein the one or more locations comprises a region of the memory, and the indication of the one or more locations comprises an indication of a start position of the region of the memory, wherein the region of memory extends from the start position over a block having a block size defined for a message authentication code,
wherein the executing the function comprises calculating the message authentication code.

Assignees

• Xilinx Inc

Inventors

• Pope Steven L
• Riddoch David J
• Fox Paul

Classifications

• G06F8/65

  Updates (security arrangements therefor G06F21/57) · CPC title

• G06F21/76

  in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD] · CPC title

• G06F21/572

  Secure firmware programming, e.g. of basic input output system [BIOS] · CPC title

• G06F21/51 Primary

  at application loading time, e.g. accepting, rejecting, starting or inhibiting executable software based on integrity or source reliability · CPC title

• H04L9/0894

  Escrow, recovery or storing of secret information, e.g. secret key escrow or cryptographic key storage · CPC title