Memory array decoding and interconnects

Patent metadata

Field	Value
Publication number	US-11501803-B2
Application number	US-202017062024-A
Country	US
Kind code	B2
Filing date	Oct 2, 2020
Priority date	Dec 18, 2018
Publication date	Nov 15, 2022
Grant date	Nov 15, 2022

Abstract

Methods and apparatuses for thin film transistors and related fabrication techniques are described. The thin film transistors may access two or more decks of memory cells disposed in a cross-point architecture. The fabrication techniques may use one or more patterns of vias formed at a top layer of a composite stack, which may facilitate building the thin film transistors within the composite stack while using a reduced number of processing steps. Different configurations of the thin film transistors may be built using the fabrication techniques by utilizing different groups of the vias. Further, circuits and components of a memory device (e.g., decoder circuitry, interconnects between aspects of one or more memory arrays) may be constructed using the thin film transistors as described herein along with related via-based fabrication techniques.

First claim

What is claimed is:

1. An apparatus, comprising:
a conductive plug that extends through a plurality of decks of memory cells;
a plurality of transistors, each transistor of the plurality of transistors comprising:
a gate electrode;
a semiconductor material at least partially surrounding the gate electrode; and
a source or a drain coupled with the conductive plug, the source or the drain comprising the semiconductor material; and

a driver coupled with the conductive plug and configured to be selectively coupled, by a transistor of the plurality of transistors, with an electrode included in a deck of the plurality of decks, wherein the electrode is coupled with the semiconductor material of the transistor.

2. The apparatus of claim 1 , further comprising:
a second conductive plug, that extends through the plurality of decks;
a second plurality of transistors that each has a source or a drain in contact with the second conductive plug; and
a second driver coupled with the second conductive plug and configured to be selectively coupled, by a subset of transistors of the second plurality, with access lines of a first type included in a subset of decks of the plurality of decks.

3. The apparatus of claim 2 , wherein the electrode comprises:
a first portion that extends between the conductive plug and the second conductive plug in a first direction;
a second portion coupled with an end of the first portion that extends in a second direction; and
a third portion coupled with a second end of the first portion that extends in the second direction.

4. The apparatus of claim 3 , wherein the first portion is wider than the second portion and the third portion.

5. The apparatus of claim 3 , wherein the gate electrodes for the plurality of transistors comprise a first plurality of gate electrodes, the apparatus further comprising:
a second plurality of gate electrodes for the second plurality of transistors, wherein the conductive plug and the second conductive plug are between the first plurality of gate electrodes and the second plurality of gate electrodes.

6. The apparatus of claim 1 ,
wherein the gate electrodes of the plurality of transistors are coupled with one another and with a common gate driver that is below the plurality of decks.

7. The apparatus of claim 1 , further comprising:
decoder circuitry below the plurality of decks and configured to activate the transistor based at least in part on selecting the gate electrode of the transistor.

8. The apparatus of claim 1 , wherein:
the gate electrode of the transistor is at a second layer of the deck; and
the semiconductor material of the transistor is coupled with the electrode via a first segment of ohmic material at a first layer of the deck and coupled with the conductive plug via a second segment of ohmic material at a third layer of the deck.

9. An apparatus, comprising:
a first region above a substrate, the first region comprising a plurality of decks of memory cells, each deck of memory cells comprising a respective plurality of array electrodes extending in a first direction; and
a second region above the substrate, the second region comprising:
a plurality of conductive plugs extending in a second direction different than the first direction; and
a respective set of transistors for each conductive plug of the plurality of conductive plugs, each transistor of the respective set of transistors corresponding to a respective deck of the plurality of decks, wherein each transistor of the respective set of transistors is configured to selectively couple a corresponding array electrode of the respective deck with a corresponding conductive plug, and wherein each transistor of the respective set of transistors comprises:
a gate electrode; and
a semiconductor material at least partially surrounding the gate electrode, the semiconductor material coupled with the corresponding array electrode of the respective deck.

10. The apparatus of claim 9 , wherein at least one transistor of the respective set of transistors is above at least one deck of the plurality of decks.

11. The apparatus of claim 9 , further comprising:
a gate select line corresponding to the respective deck, wherein the gate select line is coupled with respective gate electrodes of a plurality of transistors corresponding to the respective deck, each transistor of the plurality of transistors for a different conductive plug of the plurality of conductive plugs.

12. The apparatus of claim 9 , wherein the respective set of transistors corresponding to the respective deck are configured to be concurrently activated based at least in part on a signal carried by a respective gate electrode.

13. The apparatus of claim 9 , further comprising:
a respective driver for each conductive plug of the plurality of conductive plugs, wherein the respective driver is configured to drive an array electrode within a selected deck of the plurality of decks based at least in part on the array electrode being coupled with the corresponding conductive plug by one or more transistors of the respective set of transistors for the corresponding conductive plug.

14. The apparatus of claim 9 , further comprising:
a respective second conductive plug for each conductive plug of the plurality of conductive plugs, the respective second conductive plug within the second region; and
a respective set of second transistors for each of the second conductive plugs, wherein each second transistor of the respective set of second transistors corresponds to a respective deck of the plurality of decks, and wherein a second transistor of the respective set of second transistors is configured to:
isolate an array electrode of the respective deck from the corresponding second conductive plug when the array electrode is coupled with the corresponding conductive plug by a corresponding transistor of the respective set of transistors for the corresponding conductive plug; and
couple the array electrode with the corresponding second conductive plug when the array electrode is isolated from the corresponding conductive plug by the corresponding transistor of the respective set of transistors for the corresponding conductive plug.

15. The apparatus of claim 14 , further comprising:
a first driver coupled with the corresponding conductive plug, wherein the first driver is configured to activate the array electrode; and
a second driver coupled with the corresponding second conductive plug, wherein the second driver is configured to deactivate the array electrode.

16. The apparatus of claim 9 , further comprising:
a third region above the substrate, the first region located in between the second region and the third region, wherein the third region comprises:
an additional plurality of conductive plugs extending in the second direction different than the first direction; and
a respective set of additional transistors for each additional conductive plug of the plurality of additional conductive plugs, wherein each additional transistor of the respective set of additional transistors corresponds to a respective deck of the plurality of decks, and wherein each additional transistor of the respective set of additional transistors is configured to selectively couple the corresponding array electrode of the respective deck with a corresponding additional conductive plug.

17. An apparatus, comprising:
a first region above a substrate, the first region comprising a plurality of decks of memory cells; and
a second region above the substrate, the second region comprising a plur

Assignees

• Micron Technology Inc

Inventors

• Castro Hernan A
• Russell Stephen W
• Tang Stephen H

Classifications

• H10W72/00

  Interconnections or connectors in packages · CPC title

• H10N70/20

  Multistable switching devices, e.g. memristors · CPC title

• H10D30/67

  Thin-film transistors [TFT] {(Stacked nanowire, nanosheet or nanoribbon FETs H10D30/501)} · CPC title

• H10N70/00

  Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching (integrated devices or assemblies of multiple devices H10N79/00) · CPC title

• H10N79/00

  Integrated devices, or assemblies of multiple devices, comprising at least one solid-state element covered by group H10N70/00 (ReRAM devices H10B63/00; PCRAM devices H10B63/10) · CPC title