Analog to digital converter with floating digital channel configuration

Patent metadata

Field	Value
Publication number	US-11496148-B2
Application number	US-202117242728-A
Country	US
Kind code	B2
Filing date	Apr 28, 2021
Priority date	Mar 17, 2021
Publication date	Nov 8, 2022
Grant date	Nov 8, 2022

Abstract

One or more systems and/or methods for implementing an analog-to-digital converter system with a floating digital channel configuration are provided. An analog input component is configured to receive measured analog signals, and output analog signals, corresponding to the measured analog signals, to an analog channel coupled to the analog input component. The analog channel is coupled to a switching component connected to a first digital channel and a second digital channel. The analog channel comprises a modulator configured to convert the analog signals into a data stream selectively input by the switching component to the first digital channel or the second digital channel.

First claim

What is claimed is:

1. A system, comprising:
an analog input component configured to receive measured analog signals and output analog signals, corresponding to the measured analog signals, to a first analog channel coupled to the analog input component; and
the first analog channel coupled to a switching component connected to a first digital channel and a second digital channel, wherein the first analog channel comprises a modulator configured to convert the analog signals into a data stream selectively input by the switching component to the first digital channel or the second digital channel, wherein the first digital channel comprises a first decimator configured to convert the data stream from having a first resolution and a first sample rate to a first output data stream having a second resolution and a second sample rate different than the first resolution and the first sample rate.

2. The system of claim 1 , wherein the first analog channel is coupled to one or more additional digital channels through the switching component.

3. The system of claim 1 , comprising:
a second analog channel coupled to at least one of the first digital channel, the second digital channel, or one or more additional digital channels through the switching component.

4. The system of claim 1 , wherein the first digital channel comprises a compensation component configured to utilize offset and gain coefficient parameters.

5. The system of claim 1 , wherein, after the first decimator converts the data stream to the first output data stream, a first state of the first decimator is stored and the data stream is switched from being input into the first digital channel to being input into the second digital channel for processing by a second decimator of the second digital channel to convert the data stream from having the first resolution and the first sample rate to a second output data stream having a third resolution and a third sample rate different than the first resolution and the first sample rate.

6. The system of claim 5 , wherein, after the second decimator converts the data stream to the second output data stream, a second state of the second decimator is stored and the data stream is switched from being input into the second digital channel to being input into the first digital channel for processing by the first decimator.

7. The system of claim 1 , wherein the first digital channel comprises a first component configured to perform a function that processes the data stream based upon a first set of parameters, and wherein the second digital channel comprises a second component configured to perform a second function to process the data stream based upon a second set of parameters, wherein the second set of parameters comprises at least one parameter different than parameters of the first set of parameters.

8. The system of claim 7 , wherein the first component comprises at least one of a compensation component configured to utilize offset and gain coefficient parameters as the first set of parameters, a filter component configured to utilize filter control parameters as the first set of parameters, or a threshold comparison component configured to utilize comparison coefficient parameters as the first set of parameters.

9. A method comprising:
initializing a first decimator, of a first digital channel coupled to a switching component connected to an analog channel, to process a data stream input from a modulator of the analog channel through the switching component to the first digital channel;
initializing a second decimator, of a second digital channel coupled to the switching component connected to the analog channel, to process the data stream input from the modulator of the analog channel through the switching component to the second digital channel; and
in response to determining that the data stream is to be switched from being input into the first digital channel to being input into the second digital channel:
storing a first state of the first decimator; and
modifying a switching state of the switching component to switch the data stream from being input into the first digital channel to being input into the second digital channel after the switching state of the switching component inputs the data stream into the first digital channel.

10. The method of claim 9 , comprising:
storing a second state of the decimator based upon a determination that the data stream is to be switched from being input into the second digital channel to being input into the first digital channel.

11. The method of claim 9 , comprising:
in response to determining that the data stream is to be switched from being input into the second digital channel to being input into the first digital channel a second time:
storing a second state of the second decimator; and
modifying the switching state of the switching component to switch the data stream from being input into the second digital channel to being input into the first digital channel.

12. The method of claim 11 , comprising:
in response to determining that the data stream is to be switched from being input into the first digital channel the second time to being input into the second digital channel a second time:
storing a third state of the first decimator; and
modifying the switching state of the switching component to switch the data stream from being input into the first digital channel to being input into the second digital channel.

13. The method of claim 9 , wherein the initializing the second decimator comprises:
restoring a saved state of the second decimator to the second decimator.

14. The method of claim 9 , comprising:
in response to determining that the data stream is to be switched from being input into the first digital channel to being input into the second digital channel, implementing one or more blanking intervals before modifying the switching state of the switching component to switch the data stream from being input into the first digital channel to being input into the second digital channel.

15. The method of claim 9 , comprising:
switching the first digital channel from processing the data stream of the analog channel to processing a different data stream of a different analog channel.

16. A method comprising:
applying a first set of parameters to a component of a digital channel to initialize the component to perform a first type of processing upon a data stream input into the digital channel by a modulator of an analog channel; and
in response to determining that the component is to perform a second type of processing upon the data stream, applying a second set of parameters, comprising at least one parameter different than parameters of the first set of parameters, to the component to initialize the component to perform the second type of processing upon the data stream, wherein the component comprises a decimator, wherein the first set of parameters comprises a first set of decimator control parameters, and wherein the second set of parameters comprises a second set of decimator control parameters comprising at least one decimator control parameter different than decimator control parameters of the first set of decimator control parameters.

17. The method of claim 16 , wherein the digital channel comprise a filter component configured to utilize filter control parameters.

18. The method of claim 16 , wherein the first set of parameters are tuned to process a first type of data by the component and the second set of parameters are tuned to process a second type of data by the

Assignees

• Cypress Semiconductor Corp

Inventors

• Mann Eric N
• Hancioglu Erhan
• Thiagarajan Eashwar
• Kutz Harold
• Richardson Jr Amsby D

Classifications

• H03M3/462 Primary

  Details relating to the decimation process (decimation filters in general H03H17/0416, H03H17/0621) · CPC title

• H03M3/458

  Analogue/digital converters using delta-sigma modulation as an intermediate step · CPC title

• H03M3/352

  of deviations from the desired transfer characteristic · CPC title

• H03M3/474

  using time-division multiplexing · CPC title

• H03M1/18

  Automatic control for modifying the range of signals the converter can handle, e.g. gain ranging · CPC title