System and method for sharing central processing unit (CPU) resources with unbalanced applications

US11494236B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11494236-B2
Application numberUS-202016867613-A
CountryUS
Kind codeB2
Filing dateMay 6, 2020
Priority dateMay 6, 2020
Publication dateNov 8, 2022
Grant dateNov 8, 2022

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method, computer program product, and computing system for monitoring utilization of each central processing unit (CPU) core of a plurality of CPU cores. An average input/output (IO) latency for an operating system thread executing on the CPU core of the plurality of CPU cores may be determined. The operating system thread IO polling cadence for the at least one operating system thread executing on at least one CPU core may be adjusted based upon, at least in part, the utilization of each CPU core of the plurality of CPU cores and the average IO latency for the operating system thread executing on each CPU core of the plurality of CPU cores.

First claim

Opening claim text (preview).

What is claimed is: 1. A computer-implemented method, executed on a computing device, comprising: monitoring, via the computing device, utilization of each central processing unit (CPU) core of a plurality of CPU cores, wherein monitoring utilization of each CPU core of a plurality of CPU cores includes: monitoring a block application utilization and monitoring a file application utilization; determining an average input/output (IO) latency for an operating system thread executing on each CPU core of the plurality of CPU cores; adjusting an operating system thread IO polling cadence for at least one operating system thread executing on at least one CPU core based upon, at least in part, the utilization of each CPU core of the plurality of CPU cores and the average IO latency for the operating system thread executing on each CPU core of the plurality of CPU cores, wherein adjusting the operating system thread IO polling cadence for the at least one operating system thread executing on at least one CPU core based upon, at least in part, the utilization of each CPU core of the plurality of CPU cores and the average IO latency for the operating system thread executing on each CPU core of the plurality of CPU cores includes: determining whether the average IO latency for the operating system thread executing on the at least one CPU core is greater than average IO latencies of other CPU cores of the plurality of CPU cores by more than a predefined IO latency threshold; determining whether the file application utilization of the at least one CPU core is greater than a predefined file application utilization threshold; and preventing at least one new block application IO request from being fetched via the operating system thread executing on the at least one CPU core of the plurality of CPU cores in response to determining that the file application utilization of the CPU core is greater than the predefined file application utilization threshold. 2. The computer-implemented method of claim 1 , adjusting the operating system thread IO polling cadence for the at least one operating system thread executing on at least one CPU core based upon, at least in part, the utilization of each CPU core of the plurality of CPU cores and the average IO latency for the operating system thread executing on each CPU core of the plurality of CPU cores includes: determining whether an average block application utilization of the plurality of CPU cores is less than a first predefined block application utilization threshold. 3. The computer-implemented method of claim 2 , wherein adjusting the operating system thread IO polling cadence for the at least one operating system thread executing on at least one CPU core based upon, at least in part, the utilization of each CPU core of the plurality of CPU cores and the average IO latency for the operating system thread executing on each CPU core of the plurality of CPU cores includes: decreasing the operating system thread IO polling cadence for the at least one operating system thread executing on the at least one CPU core in response to determining that the average IO latency for the operating system thread executing on the CPU core is greater than the average IO latencies of the other CPU cores of the plurality of CPU cores by more than a predefined IO latency threshold and that the average block application utilization of the plurality of CPU cores is less than the predefined block application utilization threshold. 4. The computer-implemented method of claim 3 , wherein adjusting the operating system thread IO polling cadence for the at least one operating system thread executing on at least one CPU core based upon, at least in part, the utilization of each CPU core of the plurality of CPU cores and the average IO latency for the operating system thread executing on each CPU core of the plurality of CPU cores includes: determining whether the block application utilization of one or more CPU cores is greater than a second predefined block application utilization threshold; and increasing the operating system thread IO polling cadence for each operating system thread executing on one or more other CPU cores in response to determining that the block application utilization of the one or more CPU cores is greater than the second predefined block application utilization threshold. 5. A computer program product residing on a non-transitory computer readable medium having a plurality of instructions stored thereon which, when executed by a processor, cause the processor to perform operations comprising: monitoring utilization of each central processing unit (CPU) core of a plurality of CPU cores, wherein monitoring utilization of each CPU core of a plurality of CPU cores includes: monitoring a block application utilization and monitoring a file application utilization; determining an average input/output (IO) latency for an operating system thread executing on the CPU core of the plurality of CPU cores; adjusting an operating system thread IO polling cadence for at least one operating system thread executing on at least one CPU core based upon, at least in part, the utilization of each CPU core of the plurality of CPU cores and the average IO latency for the operating system thread executing on each CPU core of the plurality of CPU cores, wherein adjusting the operating system thread IO polling cadence for the at least one operating system thread executing on at least one CPU core based upon, at least in part, the utilization of each CPU core of the plurality of CPU cores and the average IO latency for the operating system thread executing on each CPU core of the plurality of CPU cores includes: determining whether the average IO latency for the operating system thread executing on the at least one CPU core is greater than average IO latencies of other CPU cores of the plurality of CPU cores by more than a predefined IO latency threshold; determining whether the file application utilization of the at least one CPU core is greater than a predefined file application utilization threshold; and preventing at least one new block application IO request from being fetched via the operating system thread executing on the at least one CPU core of the plurality of CPU cores in response to determining that the file application utilization of the CPU core is greater than the predefined file application utilization threshold. 6. The computer program product of claim 5 , wherein adjusting the operating system thread IO polling cadence for the at least one operating system thread executing on at least one CPU core based upon, at least in part, the utilization of each CPU core of the plurality of CPU cores and the average IO latency for the operating system thread executing on each CPU core of the plurality of CPU cores includes: determining whether an average block application utilization of the plurality of CPU cores is less than a first predefined block application utilization threshold. 7. The computer program product of claim 6 , wherein adjusting the operating system thread IO polling cadence for the at least one operating system thread executing on at least one CPU core based upon, at least in part, the utilization of each CPU core of the plurality of CPU cores and the average IO latency for the operating system thread executing on each CPU core of the plurality of CPU cores includes: decreasing the operating system thread IO polling cadence for the at least one operating system thread executing on at least one CPU core in response to determining that the average IO latency for the operating system thread executing on the CPU core is greater than the average IO latencies of the other CPU cores of the plurality of CPU cores by more than a predefined IO latency threshold

Assignees

Inventors

Classifications

  • G06F9/5027Primary

    the resource being a machine, e.g. CPUs, Servers, Terminals · CPC title

  • where the computing system component is a central processing unit [CPU] · CPC title

  • Thread allocation · CPC title

  • where the computing system is distributed, e.g. networked systems, clusters, multiprocessor systems (multiprogramming arrangements G06F9/46; allocation of resources G06F9/50) · CPC title

  • Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues · CPC title

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What does patent US11494236B2 cover?
A method, computer program product, and computing system for monitoring utilization of each central processing unit (CPU) core of a plurality of CPU cores. An average input/output (IO) latency for an operating system thread executing on the CPU core of the plurality of CPU cores may be determined. The operating system thread IO polling cadence for the at least one operating system thread execut…
Who is the assignee on this patent?
Emc Ip Holding Co Llc, EMP IP Holding Company LLC
What technology area does this patent fall under?
Primary CPC classification G06F9/5027. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Nov 08 2022 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).