Time slack application pipeline balancing for multi/many-core plcs

Patent metadata

Field	Value
Publication number	US-2015121396-A1
Application number	US-201314394395-A
Country	US
Kind code	A1
Filing date	Apr 19, 2013
Priority date	Apr 19, 2012
Publication date	Apr 30, 2015
Grant date	—

Abstract

A method for performing time-slack pipeline balancing for multi/many-core programmable logic controllers includes performing ( 411 ) a runtime analysis of a plurality multi/many-core programmable logic controller (PLC) while the program is being executed, and of a plurality of system services, to compile a profile of performance statistics of the PLC program and the system services, ( 413 ) calculating a time slack for each of the plurality of pipeline stages of the PLC program using the profile of performance statistics, and for all pipeline stages except a longest stage, donating ( 414 ) the time slack of each pipeline stage to an operating system of the PLC. Donating the time slack of each pipeline stage includes generating donor code that includes a set of instructions that free a processor core for a given pipeline stage for a time period identified as the time slack period.

First claim

What is claimed is:

1 . A method for performing time-slack pipeline balancing for multi/many-core programmable logic controllers, comprising the steps of:
calculating a time slack for each of a plurality of pipeline stages in a program for a multi/many-core programmable logic controller (PLC) using a result of a timing analysis of the plurality of stages of the PLC program; for all pipeline stages except a longest stage, donating the time slack of each pipeline stage to an operating system of the PLC, wherein donating the time slack of each pipeline stage comprises generating donor code that comprises a set of instructions that free a processor core for a given pipeline stage for a time period identified as the time slack period; and emitting machine-executable code for the PLC program

2 . The method of claim 1 , further comprising:
generating by a compiler a low-level intermediate representation of the PLC program, wherein said timing analysis is performed on the low-level intermediate representation; obtaining the number of pipeline stages; and partitioning the PLC program into the number of pipeline stages, wherein the time slack of each pipeline stage is calculated.

3 . The method of claim 1 , further comprising:
creating a plurality of threads corresponding to the plurality of pipeline stages and allocating each pipeline stage to a thread; and assigning each thread to a processor core of the PLC that is dedicated to executing user programs, wherein said donor code allows the operating system of the PLC to schedule system services to those processor cores of the PLC that have donated time slack, including those cores dedicated to executing user programs.

4 . The method of claim 1 , wherein the donor code for each pipeline stage includes a sleep instruction for the pipeline stage and a timer-triggered message configured to wake the pipeline stage when the time slack expires.

5 . The method of claim 4 , wherein the donor code is inserted between read instructions on an input queue.

6 . The method of claim 1 , wherein calculating a time slack for each of a plurality of pipeline stages uses execution profile data from previous runs of said PLC program.

7 . A method for performing time-slack pipeline balancing for multi/many-core programmable logic controllers, comprising the steps of:
performing a runtime analysis of a plurality of pipeline stages of a program for a multi/many-core programmable logic controller (PLC) while the program is being executed, and of a plurality of system services, to compile a profile of performance statistics of the PLC program and the system services; calculating a time slack for each of the plurality of pipeline stages of the PLC program using the profile of performance statistics; and for all pipeline stages except a longest stage, donating the time slack of each pipeline stage to an operating system of the PLC, wherein donating the time slack of each pipeline stage comprises generating donor code that comprises a set of instructions that free a processor core for a given pipeline stage for a time period identified as the time slack period.

8 . The method of claim 7 , wherein calculating a time slack for each of the plurality of pipeline stages uses a result of a compile-time timing analysis of the plurality of stages of the PLC program.

9 . The method of claim 7 , wherein said donor code allows the operating system of the PLC to re-schedule system services to those processor cores of the PLC that have donated time slack, wherein said pipelines are balanced.

10 . The method of claim 9 , further comprising performing a runtime analysis of the plurality of the balanced pipeline stages of the PLC program.

11 . The method of claim 7 , further comprising:
loading a machine-executable pipelined PLC program that includes a plurality of threads; scheduling the plurality of threads to processor cores of the multi/many-core PLC that are dedicated to executing user programs, wherein each pipeline stage is allocated to a thread; and executing the PLC program.

12 . The method of claim 7 , wherein the donor code for each pipeline stage includes a sleep instruction for the pipeline stage and a timer-triggered message configured to wake the pipeline stage when the time slack expires.

13 . The method of claim 7 , wherein the time slack for each of the plurality of pipeline stages is calculated after performance statistics of the PLC program have been obtained for a pre-determined number of execution cycles.

14 . A non-transitory program storage device readable by a computer, tangibly embodying a program of instructions executed by the computer to perform the method steps for performing time-slack pipeline balancing for multi/many-core programmable logic controllers, the method comprising the steps of:
calculating a time slack for each of a plurality of pipeline stages in a program for a multi/many-core programmable logic controller (PLC) using a result of a timing analysis of the plurality of stages of the PLC program; for all pipeline stages except a longest stage, donating the time slack of each pipeline stage to an operating system of the PLC, wherein donating the time slack of each pipeline stage comprises generating donor code that comprises a set of instructions that free a processor core for a given pipeline stage for a time period identified as the time slack period; and emitting machine-executable code for the PLC program

15 . The computer readable program storage device of claim 14 , the method further comprising:
generating by a compiler a low-level intermediate representation of the PLC program, wherein said timing analysis is performed on the low-level intermediate representation; obtaining the number of pipeline stages; and partitioning the PLC program into the number of pipeline stages, wherein the time slack of each pipeline stage is calculated.

16 . The computer readable program storage device of claim 14 , the method further comprising:
creating a plurality of threads corresponding to the plurality of pipeline stages and allocating each pipeline stage to a thread; and assigning each thread to a processor core of the PLC that is dedicated to executing user programs, wherein said donor code allows the operating system of the PLC to schedule system services to those processor cores of the PLC that have donated time slack, including those cores dedicated to executing user programs.

17 . The computer readable program storage device of claim 14 , wherein the donor code for each pipeline stage includes a sleep instruction for the pipeline stage and a timer-triggered message configured to wake the pipeline stage when the time slack expires.

18 . The computer readable program storage device of claim 17 , wherein the donor code is inserted between read instructions on an input queue.

19 . The computer readable program storage device of claim 14 , wherein calculating a time slack for each of a plurality of pipeline stages uses execution profile data from previous runs of said PLC program.

20 . A non-transitory program storage device readable by a computer, tangibly embodying a program of instructions executed by the computer to perform the method steps for performing time-slack pipeline balancing for multi/many-core programmable logic controllers, comprising the steps of:
performing a runtime analysis of a plurality of pipeline stages of a program for a multi/many-core programmable logic controller (PLC) while the program is be

Assignees

• Siemens Corp

Inventors

• Martinez Canedo Arquimedes
• Feichtinger Thomas
• Al Faruque Mohammad Abdullah

Classifications

• G06F8/4452 Primary

  Software pipelining · CPC title

• G06F9/4881

  Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues · CPC title

• G06F9/5083 Primary

  Techniques for rebalancing the load in a distributed system · CPC title