Gate stack design for gan e-mode transistor performance
US-2019221660-A1 · Jul 18, 2019 · US
US11489061B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-11489061-B2 |
| Application number | US-201816139248-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 24, 2018 |
| Priority date | Sep 24, 2018 |
| Publication date | Nov 1, 2022 |
| Grant date | Nov 1, 2022 |
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A transistor comprises a base layer that includes a channel region, wherein the base layer and the channel region include group III-V semiconductor material. A gate stack is above the channel region, the gate stack comprises a gate electrode and a composite gate dielectric stack, wherein the composite gate dielectric stack comprises a first large bandgap oxide layer, a low bandgap oxide layer, and a second large bandgap oxide layer to provide a programmable voltage threshold. Source and drain regions are adjacent to the channel region.
Opening claim text (preview).
What is claimed is: 1. A radio frequency (RF) switch transistor, comprising: a base layer that includes a channel region, the channel region rising above the base layer, wherein the base layer and the channel region include group III-V semiconductor material; a polarization layer over the channel region, the polarization layer having a first recess in a top of the polarization layer; an insulating layer over the polarization layer, the insulating layer having a second recess over the first recess; a gate stack located within the first recess in the polarization layer and within the second recess in the insulating layer above the channel region, the gate stack comprising a gate electrode, and a composite gate dielectric stack, wherein the composite gate dielectric stack comprises a first large bandgap oxide layer, a low bandgap oxide layer, and a second large bandgap oxide layer, the composite gate dielectric stack conformal to sidewalls of the first and second recesses and a bottom of the first recess in the polarization layer, wherein the low bandgap oxide layer comprises at least one of HfO2, TiO2 and ZrO2, wherein a depth of the first recess controls a threshold voltage (VT) of the RF switch transistor; and source and drain regions adjacent to the channel region. 2. The transistor of claim 1 , wherein the base layer and the channel region comprise gallium and nitrogen. 3. The transistor of claim 1 , wherein the first large bandgap oxide layer is adjacent to the gate electrode, the second large bandgap oxide layer is on the polarization layer adjacent to the channel region, and the low bandgap oxide layer is in-between the first large bandgap oxide layer and the second large bandgap oxide layer. 4. The transistor of claim 1 , wherein the first large bandgap oxide layer and the second large bandgap oxide layer comprise at least one of SiO2 or SiN. 5. The transistor of claim 1 , wherein the first large bandgap oxide layer and the second large bandgap oxide layer have a thickness between 1 to 10 nm. 6. The transistor of claim 1 , wherein the low bandgap oxide layer has a thickness between 1 to 10 nm. 7. The transistor of claim 1 , wherein the polarization layer includes aluminum and nitrogen. 8. The transistor of claim 1 , wherein the composite gate dielectric stack switches states between a lower threshold voltage (VT,lo) and a higher threshold voltage (VT,hi), where VT,hi is greater than VT,lo. 9. A programmable radio frequency (RF) switch transistor comprising: a base layer that includes a channel region, the channel region rising above the base layer, wherein the base layer and the channel region comprise gallium and nitrogen; a polarization layer over the channel region, the polarization layer having a first recess in a top of the polarization layer; an insulating layer over the polarization layer, the insulating layer having a second recess over the first recess; a gate stack located within the first recess in the polarization layer and within the second recess in the insulating layer above the channel region, the gate stack comprising a gate electrode, and a composite gate dielectric stack, wherein the composite gate dielectric stack comprises a first large bandgap oxide layer, a second large bandgap oxide layer, and a low bandgap oxide layer in-between the first large bandgap oxide layer and the second large bandgap oxide layer, the composite gate dielectric stack conformal to sidewalls of the first and second recesses and a bottom of the first recess in the polarization layer, wherein the low bandgap oxide layer comprises at least one of HfO2, TiO2 and ZrO2, wherein a depth of the first recess controls a threshold voltage (VT) of the RF switch transistor; and source and drain (S/D) regions adjacent to the channel region. 10. The programmable RF switch transistor of claim 9 , wherein the first large bandgap oxide layer is adjacent to the gate electrode, and the second large bandgap oxide layer is on the polarization layer adjacent to the channel region. 11. The programmable RF switch transistor of claim 9 , wherein the first large bandgap oxide layer and the second large bandgap oxide layer comprise at least one of SiO2 or SiN. 12. The programmable RF switch transistor of claim 9 , wherein the first large bandgap oxide layer and the second large bandgap oxide layer have a thickness between 1 to 10 nm. 13. The programmable RF switch transistor of claim 9 , wherein the low bandgap oxide layer has a thickness between 1 to 10 nm. 14. The programmable RF switch transistor of claim 9 , wherein the polarization layer includes aluminum and nitrogen. 15. The programmable RF switch transistor of claim 9 , wherein the composite gate dielectric stack switches states between a lower threshold voltage (VT,lo) and a higher threshold voltage (VT,hi), where VT,hi is greater than VT,lo[ ]. 16. A method of fabricating a radio frequency (RF) switch transistor, the method comprising: forming a base layer that includes a channel region, the channel region rising above the base layer, wherein the base layer and the channel region include group III-V semiconductor material; forming a polarization layer over the channel region, the polarization layer having a first recess in a top of the polarization layer; forming an insulating layer over the polarization layer, the insulating layer having a second recess over the first recess forming a gate stack located within the first recess in the polarization layer and within the second recess in the insulating layer above the channel region, the gate stack comprising a gate electrode, and a composite gate dielectric stack, wherein the composite gate dielectric stack comprises a first large bandgap oxide layer, a low bandgap oxide layer, and a second large bandgap oxide layer, the composite gate dielectric stack conformal to sidewalls of the first and second recesses and a bottom of the first recess in the polarization layer, wherein the low bandgap oxide layer comprises at least one of HfO2, TiO2 and ZrO2, wherein a depth of the first recess controls a threshold voltage (VT) of the RF switch transistor; and forming source and drain regions adjacent to the channel region. 17. The method of claim 16 , wherein forming the gate stack further comprises: depositing the second large bandgap oxide layer along sidewalls and bottom of a gate trench; depositing the low bandgap oxide layer on the second large bandgap oxide layer; depositing the first large bandgap oxide layer on the low bandgap oxide layer; and filling in a remainder of the gate trench with gate electrode material. 18. The method of claim 16 , further comprising forming the first large bandgap oxide layer and the second large bandgap oxide layer using at least one of SiO2 or SiN.
Laminate layers, e.g. stacks of alternating high-k metal oxides (adhesion layers or buffer layers H10P14/6508, H10P14/6548) · CPC title
Making the insulator · CPC title
the insulator being formed after the semiconductor body, the semiconductor being a Group III-V material · CPC title
Electricity · mapped topic
Electricity · mapped topic
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