Semiconductor device including self-aligned contact and method of manufacturing the semiconductor device

Patent metadata

Field	Value
Publication number	US-11488952-B2
Application number	US-202016888209-A
Country	US
Kind code	B2
Filing date	May 29, 2020
Priority date	Jan 10, 2020
Publication date	Nov 1, 2022
Grant date	Nov 1, 2022

Abstract

A semiconductor device according to some embodiments of the disclosure may include a fin type active pattern extending in a first direction, a plurality of gate structures on the fin type active pattern and extending in a second direction different from the first direction, a plurality of inter-contact insulation patterns on respective ones of the plurality of gate structures, a plurality of interlayer insulation layers on side surfaces of the plurality of gate structures, and a plurality of contact plugs respectively between pairs of the plurality of gate structures. The fin type active pattern may include a plurality of source/drains. Lower ends of the plurality of contact plugs may contact the plurality of source/drains. The plurality of gate structures may each include a first gate metal, a second gate metal, a gate capping layer, a gate insulation layer, a first spacer, and a second spacer.

First claim

What is claimed is:

1. A semiconductor device comprising:
a fin type active pattern extending in a first direction;
a plurality of gate structures on the fin type active pattern and extending in a second direction different from the first direction;
a plurality of inter-contact insulation patterns on respective ones of the plurality of gate structures;
a plurality of interlayer insulation layers on side surfaces of the plurality of gate structures; and
a plurality of contact plugs respectively between pairs of the plurality of gate structures,
wherein the fin type active pattern comprises a plurality of source/drains,
wherein lower ends of the plurality of contact plugs contact respective ones of the plurality of source/drains,
wherein the plurality of gate structures each comprises:
a first gate metal;
a second gate metal on a side surface and a lower portion of the first gate metal;
a gate capping layer on the first gate metal and the second gate metal, wherein the gate capping layer comprises a side surface which is inclined so that an area of a horizontal cross-sectional surface thereof increases toward an upper portion thereof in a direction away from the fin type active pattern;
a gate insulation layer on a side surface and a lower portion of the second gate metal and a lower portion of a side surface of the gate capping layer;
a first spacer on a side surface of the gate insulation layer and a side surface of the gate capping layer; and
a second spacer on a side surface of the first spacer,
wherein an uppermost surface of the gate capping layer, an uppermost surface of the first spacer, and an uppermost surface of the second spacer are at a level which is higher than a lowermost surface of each of the plurality of inter-contact insulation patterns, with respect to the fin type active pattern,
wherein a top surface of the gate capping layer is concavely recessed, and
wherein a top surface of the first spacer is downward recessed towards the fin type active pattern.

2. The semiconductor device of claim 1 , wherein the second spacer comprises an internal second spacer and an external second spacer.

3. The semiconductor device of claim 1 , wherein the fin type active pattern further comprises a silicide layer between ones of the plurality of contact plugs and between ones of the plurality of source/drains.

4. A semiconductor device comprising:
a fin type active pattern that extends in a first direction;
a plurality of gate structures on the fin type active pattern and extending in a second direction different from the first direction;
a plurality of inter-contact insulation patterns on respective ones of the plurality of gate structures;
a plurality of interlayer insulation layers on side surfaces of the plurality of gate structures; and
a plurality of contact plugs respectively between pairs of the plurality of gate structures,
wherein the fin type active pattern comprises a plurality of source/drains,
wherein lower ends of the plurality of contact plugs contact respective ones of the plurality of source/drains,
wherein the plurality of gate structures each comprises:
a first gate metal;
a second gate metal on a side surface and a lower portion of the first gate metal;
a gate capping layer on the first gate metal and the second gate metal;
a gate insulation layer on a side surface and a lower portion of the second gate metal and a lower portion of a side surface of the gate capping layer;
a first spacer on a side surface of the gate insulation layer and the gate capping layer; and
a second spacer on a side surface of the first spacer,
wherein an uppermost surface of the gate capping layer, an uppermost surface of the first spacer, and an uppermost surface of the second spacer are at a level which is higher than a lowermost surface of each of the plurality of inter-contact insulation patterns, with respect to the fin type active pattern,
wherein a top surface of the gate capping layer is concavely recessed, and
wherein a top surface of the first spacer is downward recessed towards the fin type active pattern.

5. The semiconductor device of claim 4 , wherein the second spacer comprises an internal second spacer and an external second spacer.

6. The semiconductor device of claim 5 , wherein a top surface of the internal second spacer is downward recessed towards the fin type active pattern.

7. The semiconductor device of claim 6 , wherein a top surface of the external second spacer is downward recessed towards the fin type active pattern.

8. The semiconductor device of claim 4 , wherein the fin type active pattern further comprises a silicide layer between ones of the plurality of contact plugs and between ones of the plurality of source/drains.

9. The semiconductor device of claim 4 , wherein at least one of the plurality of inter-contact insulation patterns comprises a seam.

10. The semiconductor device of claim 9 , wherein two or more of the plurality of inter-contact insulation patterns each comprise a respective seam such that there is a plurality of respective seams, and at least one of the plurality of respective seams is formed vertically along a center axis of a respective one of the plurality of inter-contact insulation patterns.

11. The semiconductor device of claim 4 , wherein top surfaces of the plurality of inter-contact insulation patterns and the plurality of contact plugs are coplanar.

12. The semiconductor device of claim 4 , wherein each of the plurality of inter-contact insulation patterns and a center of the gate capping layer are substantially vertically aligned.

13. The semiconductor device of claim 4 , wherein a bottom surface of each of the plurality of inter-contact insulation patterns protrudes downward toward the first and second gate metals.

14. The semiconductor device of claim 4 , wherein each of the plurality of inter-contact insulation patterns comprises an upper portion comprising deposited silicon oxide and a lower portion comprising oxidized silicon nitride.

15. A semiconductor device comprising:
a fin type active pattern extending in a first direction;
a plurality of gate structures extending on the fin type active pattern and in a second direction different from the first direction;
a plurality of inter-contact insulation patterns on respective ones of the plurality of gate structures;
a plurality of interlayer insulation layers on side surfaces of the plurality of gate structures; and
a plurality of contact plugs between pairs of the plurality of gate structures,
wherein the fin type active pattern comprises a plurality of source/drains,
wherein lower ends of the plurality of contact plugs contact respective ones of the plurality of source/drains,
wherein the plurality of gate structures each comprises:
a first gate metal;
a second gate metal on a side surface and a lower portion of the first gate metal;
a gate capping layer on the first gate metal and the second gate metal;
a gate insulation layer on a side surface and a lower portion of the second gate metal and a lower portion of a side surface of the gate capping layer;
a first spacer on a side surface of each of the gate insulation layer and the gate capping layer;
a second spacer on a side surface of the first spacer; and
a plurality of gate layers sequentially stacked apart from one another on a lower portion of the gate insulation layer,
wherein an uppermost surface of the gate capping layer, an uppermost surface of the first spacer, and an uppermost surface of the second spacer are at a level which is higher than a lowermost surface of each of the plu

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Sanghyun
• Kang Sungwoo
• Park Jongchul
• Oh Youngmook
• Lee Jeongyun

Classifications

• H10W20/0696

  by using sacrificial placeholders, e.g. using sacrificial plugs · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/071

  of dielectric parts thereof · CPC title

• H01L29/41791

  Electricity · mapped topic

• H01L27/0886 Primary

  Electricity · mapped topic