Adjustable column address scramble using fuses

Patent metadata

Field	Value
Publication number	US-11488685-B2
Application number	US-202117308448-A
Country	US
Kind code	B2
Filing date	May 5, 2021
Priority date	Dec 20, 2019
Publication date	Nov 1, 2022
Grant date	Nov 1, 2022

Abstract

Methods, systems, and devices for adjustable column address scramble using fuses are described. A testing device may detect a first error in a first column plane of a memory array and a second error in a second column plane of the memory array. The testing device may identify a first column address of the first column plane associated with the first error and a second column address of the second column plane based on detecting the first error and the second error. The testing device may determine, for the first column plane, a configuration for scrambling column addresses of the first column plane to different column addresses of the first column plane. In some cases, the testing device may perform a fuse blow of a fuse associated with the first column plane to implement the determined configuration.

First claim

What is claimed is:

1. A method, comprising:
performing a fuse blow of a fuse associated with a column plane to implement a configuration for scrambling column addresses of the column plane to different column addresses of the column plane;
inverting, using one or more multiplexers, at least one bit of a column address of the column plane based at least in part on performing the fuse blow; and
accessing columns of the column plane based at least in part on inverting the at least one bit of the column address.

2. The method of claim 1 , further comprising:
determining that a voltage associated with the fuse fails to satisfy a threshold based at least in part on performing the fuse blow, wherein inverting the at least one bit of the column address is based at least in part on determining that the voltage fails to satisfy the threshold.

3. The method of claim 2 , further comprising:
transmitting, to a column address decoder, a value associated with the at least one bit based at least in part on determining that the voltage fails to satisfy the threshold.

4. The method of claim 2 , further comprising:
inverting at least one other bit of the column address of the column plane based at least in part on performing the fuse blow; and
transmitting, to a column address decoder, a value associated with the at least one other bit based at least in part on determining that the voltage fails to satisfy the threshold.

5. The method of claim 1 , further comprising:
determining that a voltage of the fuse satisfies a threshold based at least in part on performing the fuse blow.

6. The method of claim 5 , further comprising:
refraining from inverting at least one other bit of the column address of the column plane based at least in part on determining that the voltage satisfies the threshold.

7. The method of claim 1 , further comprising:
scrambling the column addresses of the column plane to the different column addresses of the column plane based at least in part on inverting the at least one bit of the column address of the column plane, wherein accessing the columns of the column plane is based at least in part on scrambling the column addresses.

8. The method of claim 1 , further comprising:
determining whether an error occurred in a memory array based at least in part on performing the fuse blow, wherein the configuration is based at least in part on determining that the error occurred in the memory array.

9. An apparatus, comprising:
a memory array comprising one or more column planes;
a column address decoder configured to access a column of a column plane during an access operation;
one or more fuses coupled with the column address decoder and for implementing a configuration for scrambling column addresses of the column plane to different column addresses of the column plane; and
one or more multiplexers coupled with the one or more fuses and for inverting at least one bit of a column address of the column plane.

10. The apparatus of claim 9 , wherein the one or more multiplexers comprises a first multiplexer configured to invert a first value of a first column address bit when the one or more fuses is in a first state, wherein the first value comprises the at least one bit of the column address of the column plane.

11. The apparatus of claim 10 , wherein the first multiplexer is configured to transmit, to the column address decoder, the first value when the one or more fuses is in the first state.

12. The apparatus of claim 10 , wherein the one or more multiplexers comprises a second multiplexer configured to invert a second value of a second column address bit when the one or more fuses is in the first state, wherein the second value comprises at least one other bit of the column address of the column plane.

13. The apparatus of claim 12 , wherein the second multiplexer is configured to transmit, to the column address decoder, the second value when the one or more fuses is in the first state.

14. The apparatus of claim 9 , wherein the one or more multiplexers are configured to scramble one or more bits of addresses input into the column address decoder when at least one of the one or more fuses is blown.

15. The apparatus of claim 9 , wherein the one or more multiplexers are configured to switch one or more bits of addresses input to the column address decoder according to the configuration.

16. The apparatus of claim 9 , further comprising:
a voltage source coupled with a fuse of the one or more fuses and configured to apply a voltage to the fuse to perform a fuse blow.

17. An apparatus, comprising:
a memory array comprising a column plane;
a fuse coupled with the memory array; and
a multiplexer coupled with the fuse; and
a controller coupled with the multiplexer and configured to cause the apparatus to:
perform a fuse blow of the fuse associated with the column plane to implement a configuration for scrambling column addresses of the column plane to different column addresses of the column plane;
invert, using the multiplexer, at least one bit of a column address of the column plane based at least in part on performing the fuse blow; and
access columns of the column plane based at least in part on inverting the at least one bit of the column address.

18. The apparatus of claim 17 , wherein the controller is further configured to cause the apparatus to:
determine a state of the fuse after performing the fuse blow, wherein inverting the at least one bit is based at least in part on determining the state.

19. The apparatus of claim 18 , wherein the controller is further configured to cause the apparatus to:
scramble the column address based at least in part on the state of the fuse associated with scrambling the column addresses of the column plane.

20. The apparatus of claim 17 , wherein the controller is further configured to cause the apparatus to:
apply a voltage to the fuse to perform the fuse blow, wherein inverting the at least one bit is based at least in part on applying the voltage.

Assignees

• Micron Technology Inc

Inventors

• Rehmeyer James S
• Wieduwilt Christopher G
• Raad George
• Eichmeyer Seth
• Gans Dean

Classifications

• G11C29/70

  Masking faults in memories by using spares or by reconfiguring · CPC title

• G11C17/16 Primary

  using electrically-fusible links · CPC title

• G11C2029/1806

  Address conversion or mapping, i.e. logical to physical address · CPC title

• G11C29/787 Primary

  using a fuse hierarchy · CPC title

• G11C29/78

  using programmable devices · CPC title