Neural network circuit

Patent metadata

Field	Value
Publication number	US-11487992-B2
Application number	US-201916561207-A
Country	US
Kind code	B2
Filing date	Sep 5, 2019
Priority date	Mar 22, 2017
Publication date	Nov 1, 2022
Grant date	Nov 1, 2022

Abstract

A neural network circuit that uses a ramp function as an activation function includes a memory device in which memristors serving as memory elements are connected in a matrix. The neural network circuit further includes I-V conversion amplification circuits for converting currents flowing via the memory elements into voltages, a differential amplifier circuit for performing a differential operation on outputs of two I-V conversion amplification circuits, an A-D converter for performing an A-D conversion on a result of the differential operation, and an output determine that, by referring to input signals of the differential amplifier circuit, determines whether an output signal value of the differential amplifier circuit belongs to an active region or an inactive region. Based on a determination result, the input determiner switches over the differential amplifier circuit and the A-D converter between an operating state and a standby state.

First claim

What is claimed is:

1. A neural network circuit that uses a ramp function as an activation function, the neural network circuit comprising:
a memory device including memristors being variable resistance elements connected in a matrix, wherein the memristors serve as memory elements of the memory device and the memory device is driven by a voltage applied thereto;
a plurality of current-to-voltage (I-V) conversion amplification circuits that convert currents flowing via the memory elements into voltages and output the voltages;
a differential amplifier circuit that performs a differential operation on outputs of two I-V conversion amplification circuits forming a pair included in the plurality of I-V conversion amplification circuits;
an analog-to-digital (A-D) converter that performs an A-D conversion on a result of the differential operation of the differential amplifier circuit; and
an output determiner that:
by referring to input signals of the differential amplifier circuit, performs a first determination of whether a value of an output signal of the differential amplifier circuit belongs to an active region or an inactive region according to the ramp function being a positive polarity or a negative polarity; and
based on a result of the first determination, switches over the differential amplifier circuit and the A-D converter between an operating state and a standby state.

2. The neural network circuit according to claim 1 , further comprising:
a first switch circuit that is arranged between an output terminal of one of the two I-V conversion amplifier circuits and a first input terminal of the differential amplifier circuit; and
a second switch circuit that is arranged between an output terminal of the other of the two I-V conversion amplifier circuits and a second input terminal of the differential amplifier circuit,
wherein the output determiner turns off the first switch circuit and the second switch circuit when switching over the differential amplifier circuit to the standby state.

3. The neural network circuit according to claim 1 , further comprising:
a digital-to-analog (D-A) converter that coverts input data into a voltage;
a drive amplifier that applies the voltage to the memory device; and
an input determiner that:
by referring to the input data, perform a second determination of whether a value of the input data belongs to the active region or the inactive region according to the ramp function being the positive polarity or the negative polarity; and
based on a result of the second determination, switches over the D-A converter and the drive amplifier between an operating state and a standby state.

4. The neural network circuit according to claim 3 , wherein
when the input determiner switches over the D-A converter and the drive amplifier to the standby state, the input determiner applies a reference voltage to the memory device so as not to cause power consumption in the memory device.

5. The neural network circuit according to claim 3 , wherein
in cases where the input data has a polarity bit, the input determiner refers to the polarity bit to perform the second determination.

Assignees

• Denso Corp

Inventors

• Otsuka Shigeki
• Kataeva Irina

Classifications

• G06N3/065

  Analogue means · CPC title

• H03F2203/45528

  the FBC comprising one or more passive resistors and being coupled between the LC and the IC · CPC title

• G06F7/5443

  Sum of products (for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00) · CPC title

• H03F3/45

  Differential amplifiers (differential sense amplifiers G11C7/062) · CPC title

• G06F2207/4802

  Special implementations · CPC title