Comparator circuit, comparator circuit control method, A/D conversion circuit, and display apparatus

Patent metadata

Field	Value
Publication number	US-9906212-B2
Application number	US-201715439163-A
Country	US
Kind code	B2
Filing date	Feb 22, 2017
Priority date	Dec 27, 2013
Publication date	Feb 27, 2018
Grant date	Feb 27, 2018

Abstract

A comparator circuit includes a differential circuit unit which detects a difference between two input signals, a current supply unit which supplies a current to the differential circuit unit, and a control unit which detects an operation timing of the differential circuit unit and controls the current supplied to the differential circuit unit by the current supply unit according to a detection result thereof.

First claim

What is claimed is:

1. A comparator circuit comprising:
a differential circuit configured to receive two input signals;
a current supply circuit configured to supply a first supply current or a second supply current that is greater than the first supply current to operate the differential circuit; and
a control circuit configured to detect an output from the differential circuit and to control the current supply circuit to apply and maintain for a period of time either the first supply current or the second supply current based on a timing of the detected output.

2. The comparator circuit of claim 1 , wherein the control circuit is configured to control the current supply circuit to provide the first supply current when the differential circuit is in a standby state, and to switch from the first supply current to the second supply current before the differential circuit shifts from the standby state to an operating state.

3. The comparator circuit of claim 1 , wherein the differential circuit includes a differential amplifier arranged to output a signal according to a difference between the two input signals, and a first amplifier having a first threshold voltage, to which an output signal of the differential amplifier is input.

4. The comparator circuit of claim 3 , wherein the control circuit includes a second amplifier having a second threshold voltage lower than the first threshold voltage of the first amplifier, to which the output signal of the differential amplifier is input, wherein an output from the second amplifier is coupled to the current supply circuit to control the current supply circuit to switch between the first supply current and the second supply current according to an output signal of the second amplifier.

5. The comparator circuit of claim 4 , wherein the control circuit further includes a third amplifier having a threshold voltage higher than the threshold voltage of the first amplifier, to which the output signal of the differential amplifier is input, and wherein the control circuit is configured to control the current supply circuit to switch between the first current and the second current according to the output signal of the second amplifier and an output signal of the third amplifier.

6. The comparator circuit of claim 1 , arranged to receive a projection signal as a first input signal of the two input signals and a saw-tooth control waveform as a second input signal of the two input signals.

7. The comparator circuit of claim 1 , further comprising:
a display apparatus that includes a plurality of pixels arranged in a two-dimensional matrix;
a light emitting unit associated with one pixel of the plurality of pixels; and
a driving transistor configured to receive an output from the comparator circuit and drive the light emitting unit in response to the received output from the comparator circuit.

8. The comparator circuit of claim 7 , wherein the two input signals comprise a projection signal and a control waveform, and wherein the plurality of pixels is arranged in the shape of the two-dimensional matrix in a first direction and a second direction, and the plurality of pixels is divided into P pixel blocks along the first direction, each of the P pixel blocks containing a plurality of light emitting units, and light emitting units corresponding to a first pixel block to a Pth pixel block are configured to sequentially emit light on a pixel block by pixel block basis, wherein light emitting units from two pixel blocks emit light concurrently.

9. The comparator circuit of claim 1 , wherein the current supply circuit comprises:
a first current source configured to supply the second supply current;
a current limiter configured to constrain the second supply current supplied from the first source of current to the first supply current.

10. The comparator circuit of claim 9 , further comprising a switch circuit arranged to selectively short-circuit between an input end and an output end of the current limiter, wherein the control circuit is configured to control the switch circuit to be in an OFF state when the differential circuit is in the standby state, and to be in an ON state before the differential circuit is shifted from the standby state to an operating state.

11. The comparator circuit of claim 9 , wherein the first current source includes a first transistor having a channel length corresponding to the second current, and
the current limiter includes a second transistor having a channel length longer than the channel length of the first transistor, and is connected serially to the first transistor and in parallel to the switch circuit.

12. The comparator circuit of claim 9 , wherein the first current source includes a first transistor configured to be biased at a first bias voltage at a first gate electrode to provide the second current, and
the current limiter includes a second transistor configured to be biased at a second bias voltage at a second gate electrode to constrain the second current supplied from the first transistor and provide the first current, wherein the second transistor is connected serially to the first transistor, and is connected in parallel to the switch circuit.

13. The comparator circuit of claim 1 , wherein the current supply includes a first current source arranged to provide the first current, and a second current source arranged to provide a third current that is added to the first current to provide the second current, and
the control circuit is configured to control the second current source to be in a low state when the differential circuit is in the standby state, and to be in a high state before the differential circuit shifts from the standby state to an operating state.

14. The comparator circuit of claim 13 , wherein the first current source includes a first transistor configured to be biased at a first bias voltage corresponding to the first current, and
the second source of current includes a second transistor connected in parallel to the first transistor, and is configured to output the third current at a time of the high state.

15. The comparator circuit of claim 13 , wherein the second current source is configured to selectively reduce the supply of the second current to the differential circuit during a predetermined period in which the differential circuit is in the standby state.

16. The comparator circuit of claim 13 , wherein the differential circuit includes a differential amplifier configured to output a signal according to the difference between the two input signals, and
the second current source includes a first switch circuit configured to be in a first state according to a control waveform to reduce the supply of the second current to the differential amplifier during the predetermined period.

17. The comparator circuit of claim 16 , wherein the second current source includes a second switch circuit configured to stabilize an output voltage of the differential circuit by performing an ON/OFF operation.

Assignees

• Sony Semiconductor Solutions Corp

Inventors

• Sugiyama Takaaki
• Kitamura Ken
• Yoshioka Masaki
• Kikuchi Ken

Classifications

• H03K5/2481 Primary

  with at least one differential stage · CPC title

• G09G2370/08

  Details of image data interface between the display device controller and the data line driver circuit · CPC title

• G09G2310/066

  Waveforms comprising a gently increasing or decreasing portion, e.g. ramp · CPC title

• G09G2310/0297

  Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns · CPC title

• G09G3/3233

  with pixel circuitry controlling the current through the light-emitting element · CPC title