Semiconductor memory systems with on-die data buffering

Patent metadata

Field	Value
Publication number	US-11487679-B2
Application number	US-202017081909-A
Country	US
Kind code	B2
Filing date	Oct 27, 2020
Priority date	Oct 16, 2012
Publication date	Nov 1, 2022
Grant date	Nov 1, 2022

Abstract

A semiconductor memory system includes a first semiconductor memory die and a second semiconductor memory die. The first semiconductor memory die includes a primary data interface to receive an input data stream during write operations and to deserialize the input data stream into a first plurality of data streams, and also includes a secondary data interface, coupled to the primary data interface, to transmit the first plurality of data streams. The second semiconductor memory die includes a secondary data interface, coupled to the secondary data interface of the first semiconductor memory die, to receive the first plurality of data streams.

First claim

What is claimed is:

1. A dynamic random access memory (DRAM) die, comprising:
an array of DRAM storage cells;
a secondary data interface, in a first mode of operation, to receive a first plurality of data streams from a second DRAM die during an interval associated with read operations; and
a primary data interface coupled to the secondary data interface, in the first mode of operation, to serialize the first plurality of data streams into a read data stream and to transmit the read data stream to a first integrated circuit (IC) chip.

2. The DRAM die of claim 1 , wherein:
the secondary data interface is to receive the first plurality of data streams at a first single data rate (SDR) during the time interval associated with the read operations; and
the primary data interface is to transmit the read data stream at a double data rate (DDR) during the time interval associated with the read operations.

3. The DRAM die of claim 1 , further comprising:
configuration circuitry for configuring use of the DRAM die between the first mode of operation and a second mode of operation;
wherein the DRAM die is configurable to operate as a master die for direct communication with the first IC chip in the first mode of operation and as a minion die for indirect communication with the first IC chip in the second mode of operation.

4. The DRAM die of claim 3 , wherein:
the primary data interface is configurable to serialize the first plurality of data streams into the read data stream and transmit the read data stream in the first mode of operation and to be deactivated in the second mode of operation; and
the secondary data interface is configurable to receive the first plurality of data streams during the interval associated with the read operations in the first mode of operation and to transmit a second plurality of data streams during the interval associated with the read operations in the second mode of operation.

5. The DRAM die of claim 1 , wherein:
the first IC chip comprises a memory controller IC chip.

6. The DRAM die of claim 1 , wherein:
the primary data interface comprises a first bond pad to transmit the read data stream; and
the secondary data interface comprises a second bond pad through which to receive a first data stream of the first plurality of data streams and a third bond pad through which to receive a second data stream of the first plurality of data streams.

7. The DRAM die of claim 6 , further comprising:
a plurality of through-die vias, coupled to the secondary data interface, to receive the first plurality of data streams.

8. A dynamic random access memory (DRAM) chip package, comprising:
multiple DRAM integrated circuit (IC) chips, a first one of the multiple DRAM IC chips comprising
an array of DRAM storage cells;
a secondary data interface, in a first mode of operation, to receive a first plurality of data streams from a second one of the multiple DRAM IC chips during an interval associated with read operations; and
a primary data interface coupled to the secondary data interface, in the first mode of operation, to serialize the first plurality of data streams into a read data stream and to transmit the read data stream to a memory controller.

9. The DRAM chip package according to claim 8 , wherein:
the secondary data interface is to receive the first plurality of data streams at a first single data rate (SDR) during the time interval associated with the read operations; and
the primary data interface is to transmit the read data stream at a double data rate (DDR) during the time interval associated with the read operations.

10. The DRAM chip package according to claim 8 , wherein each of the multiple DRAM IC chips further comprises:
configuration circuitry for configuring use of a corresponding DRAM IC chip between the first mode of operation and a second mode of operation;
wherein each of the multiple DRAM IC chips is configurable to operate as a master die for direct communication with the memory controller in the first mode of operation and as a minion die for indirect communication with the memory controller in the second mode of operation.

11. The DRAM chip package according to claim 10 , wherein:
the first DRAM IC chip of the multiple DRAM IC chips operates in the first mode of operation; and
the other of the multiple DRAM IC chips operate in the second mode of operation.

12. The DRAM chip package according to claim 10 , wherein for each of the multiple DRAM IC chips:
the primary data interface is configurable to serialize the first plurality of data streams into the read data stream and transmit the read data stream in the first mode of operation and to be deactivated in the second mode of operation; and
the secondary data interface is configurable to receive the first plurality of data streams during the interval associated with the read operations in the first mode of operation and to transmit a second plurality of data streams during the interval associated with the read operations in the second mode of operation.

13. The DRAM chip package according to claim 8 , wherein for each of the multiple DRAM IC chips:
the primary data interface comprises a first bond pad to transmit the read data stream in the first mode of operation; and
the secondary data interface comprises a second bond pad through which to receive a first data stream of the first plurality of data streams and a third bond pad through which to receive a second data stream of the first plurality of data streams.

14. The DRAM IC chip package according to claim 13 , wherein each of the multiple DRAM IC chips further comprises:
a plurality of through-die vias, coupled to the secondary data interface, to receive the first plurality of data streams.

15. A method of operation in a dynamic random access memory (DRAM) integrated circuit (IC) chip, the DRAM IC chip including an array of DRAM storage cells, the method comprising:
in a first mode of operation
receiving a first plurality of data streams with a secondary interface, the first plurality of data streams from a second DRAM IC chip during an interval associated with read operations;
serializing, with a primary data interface, the first plurality of data streams into a read data stream; and
transmitting the read data stream to a first integrated circuit (IC) chip.

16. The method according to claim 15 , wherein:
the receiving of the first plurality of data streams is carried out at a first single data rate (SDR) during the time interval associated with the read operations; and
the transmitting of the read data stream is carried out at a double data rate (DDR) during the time interval associated with the read operations.

17. The method according to claim 15 , further comprising:
configuring use of the DRAM IC chip between the first mode of operation and a second mode of operation; and
operating the DRAM IC chip as a master die for direct communication with the first IC chip in the first mode of operation and as a minion die for indirect communication with the first IC chip in the second mode of operation.

18. The method according to claim 17 , wherein:
the primary data interface is configurable to serialize the first plurality of data streams into the read data stream and transmit the read data stream in the first mode of operation and to be deactivated in the second mode of operation; and
the secondary data interface is configurable to receive the first plurality of data streams during the interval associated with the read operations in the first mode of operation

Assignees

• Rambus Inc

Inventors

• Ware Frederick A
• Amirkhany Amir
• Rajan Suresh
• Hekmat Mohammad
• Patil Dinesh

Classifications

• G11C7/1066

  Output synchronization · CPC title

• G11C7/1012

  Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating · CPC title

• G11C29/022

  in I/O circuitry · CPC title

• G06F13/1673 Primary

  using buffers · CPC title

• G11C7/1093

  Input synchronization · CPC title