Programmable integrated circuit with stacked memory die for storing configuration data

Patent metadata

Field	Value
Publication number	US-11487445-B2
Application number	US-201615358738-A
Country	US
Kind code	B2
Filing date	Nov 22, 2016
Priority date	Nov 22, 2016
Publication date	Nov 1, 2022
Grant date	Nov 1, 2022

Abstract

A system may include a host processor, a coprocessor for accelerating tasks received from the host processor, and one or more memory dies mounted to the coprocessor. The coprocessor and the memory die may be part of an integrated circuit package. The memory die may convey configuration bit streams to one or more logic sectors in programmable circuitry of the coprocessor over through-silicon vias. Each logic sector may include one or more data registers that are loaded with configuration data from the memory die. Multiple data registers may be loaded with configuration data simultaneously. The configuration data may be loaded onto an array of configuration memory cells using the data registers. Multiple data registers may be pipelined to allow simultaneous loading of configuration data into multiple sub-arrays of the array of configuration memory cells.

First claim

What is claimed is:

1. An integrated circuit package, comprising:
an integrated circuit that includes a substrate and programmable circuitry having a plurality of programmable circuitry configuration controllers to configure different respective portions of the programmable circuitry formed on a first plane of the substrate;
a first external memory die that is mounted directly on a second plane of the substrate of the integrated circuit opposite the first plane of the substrate of the integrated circuit and that is stacked directly opposite and is coupled to a first programmable circuitry configuration controller of the plurality of the programmable circuitry configuration controllers, wherein the first programmable circuitry configuration controller is placed within width range of the first external memory die on the first plane; and
a second external memory die that is mounted directly on the second plane of the substrate of the integrated circuit and that is stacked directly opposite and is coupled to a second programmable circuitry configuration controller of the plurality of the programmable circuitry configuration controllers, wherein the second programmable circuitry configuration controller is placed within width range of the second external memory die on the first plane, wherein the first and second external memory dies are mounted in the same plane over the integrated circuit.

2. The integrated circuit package of claim 1 , wherein the integrated circuit includes through-silicon vias formed through the substrate through which configuration bit streams are conveyed from the first and second external memory dies to the programmable circuitry.

3. The integrated circuit package of claim 2 , wherein the programmable circuitry configuration controllers are configured to retrieve the configuration bit streams from the first and second external memory dies.

4. The integrated circuit package of claim 3 , wherein a first portion of the respective portions of the programmable logic circuitry comprises:
an array of memory cells;
an address register coupled to the array of memory cells; and
a data register coupled to the array of memory cells, wherein the data register is also coupled to the first external memory die through at least some of the through silicon vias.

5. The integrated circuit package of claim 3 , wherein a first portion of the respective portions of the programmable logic circuitry comprises:
a first sub-array of memory cells;
a second sub-array of memory cells;
a first data register coupled to the first sub-array of memory cells; and
a second data register coupled to the second sub-array of memory cells, wherein the first programmable circuitry configuration controller associated with the first portion of the respective portions of the programmable logic circuitry controls the first and second data registers.

6. The integrated circuit package of claim 5 , wherein the first and second data registers are configurable to load a configuration bit stream in parallel from the first external memory die.

7. The integrated circuit package of claim 5 , wherein the first data register is configurable to transfer data from the first data register to the second data register.

8. The integrated circuit package of claim 5 , wherein the first and second data registers are configurable to load a selected one of the configuration bit streams into the first and second sub-arrays of memory cells in parallel.

9. The integrated circuit package of claim 1 , comprising a transistor layer and dielectric stack formed on the substrate.

10. The integrated circuit package of claim 9 , wherein the plurality of programmable circuitry configuration controllers are included in the transistor layer and dielectric stack.

11. The integrated circuit package of claim 9 , wherein the transistor layer and dielectric stack include sectors associated with the plurality of programmable circuitry configuration controllers and electronically conductive interconnects.

12. A system, comprising:
a host processor;
a coprocessor coupled to the host processor, wherein the coprocessor comprises:
a substrate;
a first programmable circuitry region manager that is formed on a first plane of the substrate;
a first programmable circuitry region that is formed on the first plane of the substrate and that is managed by the first programmable circuitry region manager;
a second programmable circuitry region manager that is formed on the first plane of the substrate;
a second programmable circuitry region that is formed on the first plane of the substrate and that is managed by the second programmable circuitry region manager;
a first external memory die that is mounted directly on a second plane opposite the first plane of the substrate of the coprocessor and that is stacked directly opposite and is coupled to the first programmable circuitry region manager using first through-silicon vias in the substrate, wherein the first programmable circuitry region manager is placed within width range of the first external memory die on the first plane; and
a second external memory die that is mounted directly on the second plane of the substrate of the coprocessor and that is stacked directly opposite and is coupled to the second programmable circuitry region manager using second through-silicon vias in the substrate, wherein the second programmable circuitry region manager is placed within width range of the second external memory die on the first plane, wherein the first and second external memory dies are mounted in the same plane over the coprocessor.

13. A method of operating an integrated circuit package that includes a programmable logic circuitry disposed on a first plane of a substrate and a plurality of memory dies respectively stacked directly on a second plane of the substrate opposite the first plane, the method comprising:
configuring, using a first configuration controller of the programmable logic circuitry, a first region of the programmable logic circuitry to perform a first custom function,
configuring, using a second configuration controller of the programmable logic circuitry, a second region of the programmable logic circuitry to perform a second custom function;
conveying a first configuration bit stream from a first memory die of the plurality of memory dies to the first region of the programmable logic circuitry by way of through silicon vias formed in the substrate, wherein the first memory die is stacked directly opposite and is coupled to the first configuration controller and the first configuration controller is placed within width range of the first memory die on the first plane;
conveying a second configuration bit stream from a second memory die of the plurality of memory dies to second first region of the programmable logic circuitry by way of through silicon vias formed in the substrate, wherein the second memory die is stacked directly opposite and is coupled to the second configuration controller and the second configuration controller is placed within width range of the second memory die on the second plane;
reconfiguring the first region of the programmable circuitry using at least a portion of the first configuration bit stream so that the programmable circuitry is configured to perform a third custom function; and
reconfiguring the second region of the programmable circuitry using at least a portion of the second configuration bit stream so that the programmable circuitry is configured to perform a fourth custom function.

14. The method of claim 13 , wherein using the programmable logic circuitry to perform the first custom funct

Assignees

• Intel Corp

Inventors

• Dasu Aravind
• Weber Scott
• Tan Jun Pin
• Rahman Arifur

Classifications

• G06F15/7871 Primary

  Reconfiguration support, e.g. configuration loading, configuration switching, or hardware OS · CPC title

• G06F3/061

  Improving I/O performance · CPC title

• G11C5/02

  Disposition of storage elements, e.g. in the form of a matrix array · CPC title

• G06F3/0647

  Migration mechanisms · CPC title

• G11C5/06

  Arrangements for interconnecting storage elements electrically, e.g. by wiring · CPC title