Semiconductor devices and methods of fabricating the same

Patent metadata

Field	Value
Publication number	US-11482602-B2
Application number	US-202017034088-A
Country	US
Kind code	B2
Filing date	Sep 28, 2020
Priority date	Jan 10, 2020
Publication date	Oct 25, 2022
Grant date	Oct 25, 2022

Abstract

A semiconductor device is disclosed. The semiconductor device includes a gate electrode on a substrate and extending in a first direction, source/drain patterns spaced apart from each other, in a second direction, with the gate electrode interposed therebetween, a gate contact electrically connected to the gate electrode, and an active contact electrically connected to at least one of the source/drain patterns. The active contact includes a lower contact pattern electrically connected to the at least one of the source/drain patterns, the lower contact pattern having a first width in the first direction, and an upper contact pattern electrically connected to a top surface of the lower contact pattern, the upper contact pattern having a second width in the first direction that is smaller than the first width. The upper contact pattern and the gate contact horizontally overlap each other.

First claim

What is claimed is:

1. A semiconductor device comprising:
a gate electrode on a substrate and extending in a first direction;
source/drain patterns spaced apart from each other, in a second direction that intersects the first direction, with the gate electrode interposed therebetween;
a gate contact electrically connected to the gate electrode; and
an active contact electrically connected to at least one of the source/drain patterns,
wherein the active contact comprises:
a lower contact pattern electrically connected to the at least one of the source/drain patterns, the lower contact pattern having a first width in the first direction; and
an upper contact pattern electrically connected to a top surface of the lower contact pattern, the upper contact pattern having a second width in the first direction that is smaller than the first width, and

wherein the upper contact pattern and the gate contact horizontally overlap each other in a third direction that is oblique to the second direction and do not horizontally overlap each other in the second direction.

2. The semiconductor device of claim 1 ,
wherein the lower contact pattern comprises a first conductive pattern and a first barrier pattern that is on side and bottom surfaces of the first conductive pattern, and
wherein the first barrier pattern is absent from at least a portion of a top surface of the first conductive pattern.

3. The semiconductor device of claim 2 , wherein a top surface of the first barrier pattern is located at a level lower than a top surface of the upper contact pattern.

4. The semiconductor device of claim 2 ,
wherein the upper contact pattern comprises a second conductive pattern and a second barrier pattern that is on side and bottom surfaces of the second conductive pattern, and
wherein the second barrier pattern extends into a region between the second conductive pattern and the first conductive pattern.

5. The semiconductor device of claim 4 , wherein a thickness of the second barrier pattern is different from a thickness of the first barrier pattern.

6. The semiconductor device of claim 4 ,
wherein the second conductive pattern comprises aluminum, copper, tungsten, molybdenum, or cobalt, and
wherein the first conductive pattern comprises a different one of aluminum, copper, tungsten, molybdenum, or cobalt from the second conductive pattern.

7. The semiconductor device of claim 1 ,
wherein the upper contact pattern comprises a first side surface and a second side surface that are respectively inclined at first and second angles with respect to the top surface of the lower contact pattern, and
wherein the first and second angles are acute and obtuse, respectively.

8. The semiconductor device of claim 7 , wherein the first side surface is aligned with a side surface of the lower contact pattern.

9. The semiconductor device of claim 1 ,
wherein the upper contact pattern comprises a first side surface and a second side surface that are respectively inclined at first and second angles with respect to the top surface of the lower contact pattern, and
wherein both of the first and second angles are acute or both of the first and second angles are obtuse.

10. The semiconductor device of claim 1 , wherein a bottom surface of the upper contact pattern is at a level lower than a top surface of the gate electrode.

11. The semiconductor device of claim 1 ,
wherein the top surface of the lower contact pattern is at a level lower than a bottom surface of the gate contact, and
wherein the lower contact pattern extends below a bottom surface of the gate electrode and into a first source/drain pattern of the source/drain patterns.

12. The semiconductor device of claim 1 , further comprising:
a first via on the upper contact pattern; and
a second via on the gate contact,
wherein the first via and the second via horizontally overlap each other.

13. The semiconductor device of claim 1 ,
wherein the lower contact pattern comprises:
a first end portion that is adjacent to the gate contact; and
a second end portion that is opposite the first end portion in the first direction and distal from the gate contact, and

wherein the upper contact pattern is on the second end portion and is absent from the first end portion.

14. The semiconductor device of claim 1 , wherein the gate contact is between ones of the source/drain patterns that are adjacent to each other in the second direction.

15. The semiconductor device of claim 1 , further comprising a first channel pattern between the source/drain patterns,
wherein the first channel pattern comprises a plurality of first channel patterns that are vertically stacked, and
wherein the gate electrode surrounds top, bottom, and opposite side surfaces of each of the plurality of first channel patterns.

16. A semiconductor device comprising:
a gate electrode on a substrate and extending in a first direction;
source/drain patterns spaced apart from each other, in a second direction that intersects the first direction, with the gate electrode interposed therebetween;
a gate contact electrically connected to the gate electrode; and
an active contact electrically connected to at least one of the source/drain patterns,
wherein the active contact comprises a lower contact pattern electrically connected to the at least one of the source/drain patterns and an upper contact pattern electrically connected to a top surface of the lower contact pattern,
wherein the lower contact pattern comprises a first end portion proximal to the gate contact and a second end portion opposite the first end portion in the first direction and distal from the gate contact, and
wherein the upper contact pattern is on the second end portion and is absent from the first end portion.

17. The semiconductor device of claim 16 ,
wherein a horizontal plane defined by the first direction and the second direction includes both a portion of the upper contact pattern and a portion of the gate contact,
wherein, in the horizontal plane, the second end portion is spaced apart from the gate contact by a first distance in a third direction that is oblique to the first and second directions, and
wherein, in the horizontal plane, the first end portion is spaced apart from the gate contact in the second direction by a second distance that is shorter than the first distance.

18. The semiconductor device of claim 16 , further comprising:
a first via on the upper contact pattern; and
a second via on the gate contact,
wherein the first via and the second via horizontally overlap each other.

19. The semiconductor device of claim 16 ,
wherein the lower contact pattern comprises a first conductive pattern and a first barrier pattern that is on side and bottom surfaces of the first conductive pattern,
wherein the upper contact pattern comprises a second conductive pattern and a second barrier pattern that is on side and bottom surfaces of the second conductive pattern, and
wherein the second barrier pattern extends into a region between the second conductive pattern and the first conductive pattern.

20. A semiconductor device comprising:
a gate electrode extending in a first direction on an active pattern on a substrate;
source/drain patterns spaced apart from each other, in a second direction, with the gate electrode interposed therebetween;
a gate contact electrically connected to the gate electrode;
an active contact electrically connected to at least one of the source/drain patterns;
a gate in

Assignees

• Samsung Electronics Co Ltd

Inventors

• Song Hyun-Seung
• Kim Tae-Yeol
• Baek Jae-Jik

Classifications

• H10W20/0693

  by forming self-aligned vias · CPC title

• H10W20/0696

  by using sacrificial placeholders, e.g. using sacrificial plugs · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/033

  in openings in dielectrics · CPC title