Variable resistive memory device and method of driving a variable resistive memory device

Patent metadata

Field	Value
Publication number	US-11482283-B2
Application number	US-202117214592-A
Country	US
Kind code	B2
Filing date	Mar 26, 2021
Priority date	Jul 19, 2018
Publication date	Oct 25, 2022
Grant date	Oct 25, 2022

Abstract

A variable resistive memory device includes a memory cell, a first circuit, and a second circuit. The memory cell is connected between a word line and a bit line. The first circuit provides the bit line with a first pulse voltage based on at least one enable signal. The second circuit provides the word line with a second pulse voltage based on the enable signal. The first circuit generates the first pulse voltage increased in steps from an initial voltage level to a target voltage level.

First claim

What is claimed is:

1. A variable resistive memory device comprising:
a memory cell array including a plurality of memory cells, each of the memory cells including a plurality of word lines, a plurality of bit lines, and a resistance layer connected between the word lines and the bit lines; and
a control block for selecting a selected memory cell among the plurality of memory cells, for applying a voltage between a selected bit line among the plurality of bit lines and a selected word line among the plurality of word lines connected with the selected memory cell to generate a minimum voltage difference for turning-on the selected memory cell, and for gradually increasing in steps the voltage applied to the selected bit line to a target voltage level when the selected memory cell is turned-on.

2. The variable resistive memory device of claim 1 , wherein the control block comprises:
a signal control circuit for providing an initial voltage based on a write enable signal and for outputting a voltage increased in steps to a target voltage level based on a detection signal generated when the memory cell is turned on; and
a first signal selection circuit for selecting any one of the bit lines in response to a column selection signal and for transferring a voltage outputted from the signal control circuit to the selected bit line.

3. The variable resistive memory device of claim 2 , wherein the control block further comprises:
a current control circuit for providing an initial current based on the write enable signal and for providing a current increased in steps to a target current level based on the detection signal; and
a second signal selection circuit for selecting any one of the word lines in response to a row selection signal and for transferring a current provided from the current control circuit to the selected word line.

4. The variable resistive memory device of claim 3 , wherein the control block further comprises:
a detection circuit connected with the second signal selection circuit, the detection circuit for detecting a current amount of the selected memory cell to output the detection signal; and
a control circuit for generating the write enable signal, the column selection signal, and the row selection signal and for generating control signals for controlling the signal control circuit and the current control circuit based on the detection signal.

5. The variable resistive memory device of claim 4 , wherein the detection circuit comprises:
a sense amplifier for detecting a timing at which a current of the selected memory cell is increased to no less than a critical current to output a pre-detection signal; and
a latch for latching the pre-detection signal.

6. The variable resistive memory device of claim 1 , wherein the first signal selection circuit comprises:
a global bit line switch connected to the signal control circuit to transfer an output signal of the signal control circuit in response to a global bit line selection signal of the column selection signal; and
a local bit line switch connected to the global bit line switch to transfer a signal transmitted through the global bit line switch to the selected bit line in response to a local bit line selection signal of the column selection signal.

7. The variable resistive memory device of claim 3 , wherein the second signal selection circuit comprises:
a global word line switch connected to the second signal control circuit to transfer an output signal of the current control circuit in response to a global word line selection signal of the row selection signal; and
a local word line switch connected to the global word line switch to transfer a signal transmitted through the global word line switch to the selected word line in response to a local word line selection signal of the row selection signal.

8. The variable resistive memory device of claim 7 , wherein the control block further comprises a switch drive circuit for decreasing a level of the local word line selection signal to a low voltage level before the target current level, and wherein the low voltage level is lower than a normal level for driving the local word line switch and higher than a critical level for driving the local word line switch.

9. A method of driving a variable resistive memory device, the method comprising writing to the variable resistive memory device, wherein the variable resistive memory device comprises a memory cell connected between a word line and a bit line, wherein the writing comprises:
applying a first word line selection voltage to the word line and applying an initial voltage to the bit line in response to a write enable signal to provide a voltage difference between the word line and the bit line with a minimum voltage difference for turning on the memory cell;
detecting the turning on of the memory cell while the word line and the bit line have the minimum voltage difference; and
applying a write voltage to the bit line based on detection results,
wherein the write voltage is gradually increased in steps from the initial voltage to a target write voltage level in response to the detection results.

10. The method of claim 9 , wherein applying the initial voltage further comprises applying an additional initial voltage, which is higher than the initial voltage, to the bit line when the memory cell is not turned on after applying the initial voltage, and the additional initial voltage is lower than the target write voltage level.

Assignees

• Sk Hynix Inc

Inventors

• Lee Ki Won
• Hong Seok Man
• Kim Tae Hoon
• Lee Hyung Dong

Classifications

• G11C13/0028

  Word-line or row circuits · CPC title

• G11C13/0069

  Writing or programming circuits or methods · CPC title

• G11C13/0038 Primary

  Power supply circuits · CPC title

• G11C11/1675

  Writing or programming circuits or methods · CPC title

• G11C11/1655 Primary

  Bit-line or column circuits · CPC title