Memory module adapted to implementing computing functions

Patent metadata

Field	Value
Publication number	US-11482264-B2
Application number	US-202117645527-A
Country	US
Kind code	B2
Filing date	Dec 22, 2021
Priority date	Dec 28, 2020
Publication date	Oct 25, 2022
Grant date	Oct 25, 2022

Abstract

The present description concerns a memory device (200) comprising: a memory circuit (201) implementing operations and performing elementary operations including a reading, a writing, or a computing operation; a control circuit (205) receiving instructions from a processor (231), and breaking down each received instruction into a plurality of elementary operations to generate an elementary operation request flow; a circuit (203) of direct data transfer from or to said memory circuit (201), the transfer circuit (203) receiving instructions from the processor (231), breaking down each received instruction into a plurality of elementary operations to be performed in said memory circuit to generate an elementary operation request flow; an internal data exchange link (204) directly coupling said memory circuit (201) to the direct transfer circuit (203); and an arbitration circuit (309).

First claim

What is claimed is:

1. Memory device comprising:
a port of connection of the device to a processor;
a memory circuit adapted to implementing computing operations and to carrying out elementary operations including a reading, a writing, or a computing operation;
a first control circuit adapted to receiving first instructions from the processor via said port, and of breaking down each first received instruction into a sequence of one or a plurality of elementary operations to generate a first elementary operation request flow;
a circuit of direct data transfer from or to said memory circuit, the direct transfer circuit being adapted to receiving second instructions from the processor via said port, of breaking down each second received instruction into a sequence of a plurality of elementary operations to be performed in said memory circuit to generate a second elementary operation request flow;
an internal data exchange link directly coupling said memory circuit to the direct transfer circuit; and
an arbitration circuit adapted to receiving the first and second elementary operation request flows and of controlling the first control circuit to execute a single general elementary operation request flow in the memory circuit by implementing predefined priority rules in the case of simultaneous requests for access to the memory circuit,
wherein the internal link has a data width greater than the data width of the port of connection of the device to the processor.

2. Memory device according to claim 1 , wherein the direct transfer circuit comprises a buffer circuit adapted to temporarily storing data transiting from or to said memory circuit.

3. Memory device according to claim 1 , comprising a distribution circuit) connected to said port of connection of the device to the processor, the distribution circuit receiving the first and second instructions from the processor and being adapted to transmitting the first instructions to the first control circuit and the second instructions to the direct transfer circuit, the distribution circuit using address information present in the instruction to perform this distribution.

4. Memory device according to claim 1 , wherein the internal link has a data width equal to the size of the largest data vector capable of being read at once from said memory circuit.

5. Memory device according to claim 1 , wherein the internal link has a data width at least twice greater than the data width of the port of connection of the device to the processor.

6. Memory device according to claim 1 , wherein the direct transfer circuit is connected to a port of connection of the module to a memory system bus external to the device.

7. Memory device according to claim 6 , wherein the port of connection of the device to the memory system bus has a data width greater than the data width of the port of connection of the device to the processor.

8. Memory device according to claim 2 , wherein the direct transfer circuit is connected to a port of connection of the module to a memory system bus external to the device, and wherein the buffer circuit of the direct transfer circuit is adapted to temporarily storing data transiting between said memory circuit and an external memory circuit coupled to said memory system bus.

9. Memory device according to claim 1 , wherein the direct transfer circuit comprises configuration registers storing the second instructions received from the processor.

10. Memory device according to claim 8 , wherein the direct transfer circuit further comprises a second control circuit adapted to reading from and writing into the configuration registers, to exchanging control data with the arbitration circuit, and to controlling data transfers via the buffer circuit.

11. Memory device according to claim 1 , wherein said memory circuit comprises a plurality of memory circuits adapted to implementing computing operations, said memory circuits being arranged in an array of rows and columns.

12. Memory device according to claim 11 , wherein the array of memory circuits is reconfigurable to adjust the dimensions of the data vectors in the row direction.

13. System comprising the memory device of claim 1 , a processor adapted to transmitting the first and second instructions to the memory device, a memory system bus coupled to the direct transfer circuit of the memory device, and an external memory circuit coupled to the memory system bus, wherein the direct transfer circuit is adapted to transferring data directly between the memory circuit of the device and the external memory circuit via the memory system bus, without transiting through the processor.

Assignees

• Commissariat Energie Atomique

Inventors

• Kooli Maha
• Gauchi Roman
• Vivet Pascal

Classifications

• G11C7/1039

  using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers · CPC title

• G11C7/1096 Primary

  Write circuits, e.g. I/O line write drivers · CPC title

• G06F13/1605

  based on arbitration (arbitration in handling access to a common bus or bus system G06F13/36) · CPC title

• G11C7/1069

  I/O lines read out arrangements · CPC title

• G11C7/1006 Primary

  Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor · CPC title