Configurable integrated circuit (ic) with cyclic redundancy check (crc) arbitration

Patent metadata

Field	Value
Publication number	US-2021191805-A1
Application number	US-202017128595-A
Country	US
Kind code	A1
Filing date	Dec 21, 2020
Priority date	Dec 20, 2019
Publication date	Jun 24, 2021
Grant date	—

Abstract

An integrated circuit (IC) includes: a storage having a storage interface and addressable bytes, the storage interface coupled to first and second sets of peripheral terminals; control circuitry having control circuitry inputs and control circuitry outputs, the control circuitry inputs coupled to the storage interface and configured to receive configuration bits provided by the storage responsive to a control circuitry update trigger, and the control circuitry outputs coupled to first and second sets of peripheral outputs; and a cyclic-redundancy check (CRC) engine coupled to the storage interface, the CRC engine configured to distinguish between purposeful updates to the data in the storage and bit errors in the data in the storage.

First claim

What is claimed is:

1 . An integrated circuit (IC), comprising:
a first peripheral terminal adapted to be coupled to a communication terminal of a first peripheral; a first set of peripheral outputs adapted to be coupled to peripheral inputs of the first peripheral; a second peripheral terminal adapted to be coupled to a communication terminal of a second peripheral; a second set of peripheral outputs adapted to be coupled to peripheral inputs of the second peripheral; a storage having a storage interface and addressable bytes, the storage interface coupled to the first and second peripheral terminals; control circuitry having control circuitry inputs and control circuitry outputs, the control circuitry inputs coupled to the storage interface and configured to receive configuration bits from addressable bytes of the storage responsive to a control circuitry update trigger, and the control circuitry outputs coupled to the first and second sets of peripheral outputs; and a cyclic-redundancy check (CRC) engine coupled to the storage interface, the CRC engine configured to distinguish between purposeful updates to the data in the storage and bit errors in the data in the storage.

2 . The IC of claim 1 , wherein the CRC engine includes:
arbitration logic having arbitration logic inputs and an arbitration logic output, the arbitration logic inputs coupled to the first peripheral terminal, the second peripheral terminal and an internal write request source, the arbitration logic configured to provide a write request at the arbitration logic output responsive to arbitration between internal write requests from the internal write request source, external write requests from the first peripheral, and external write requests from the second peripheral; and a write queue having a write queue input coupled to the arbitration logic output.

3 . The IC of claim 2 , wherein the write queue includes a first write queue output, a second write queue output, and a third write queue output, and the CRC engine includes:
a read multiplexer having read multiplexer inputs, a read multiplexer control input, and a read multiplexer output, the read multiplexer inputs coupled to the storage interface; a data multiplexer having a first data multiplexer input, a second data multiplexer input, a data multiplexer control input, and a data multiplexer output, the first data multiplexer input coupled to the second write queue output, the second data multiplexer input coupled to the read multiplexer output, and the data multiplexer control input coupled to the first write queue output; CRC logic coupled to each of the storage interface and configured to provide a CRC checksum value for each of the addressable bytes; a CRC multiplexer having CRC multiplexer inputs, a CRC multiplexer output and a CRC multiplexer control input, the CRC multiplexer inputs coupled to the CRC logic; and multiplexer control circuitry having a set of multiplexer control outputs coupled to the read multiplexer control input, the CRC multiplexer control input and the data multiplexer control input, in which the write queue includes or is coupled to the multiplexer control circuitry.

4 . The IC of claim 3 , wherein the CRC engine includes:
current data CRC engine logic coupled to the CRC multiplexer output and the read multiplexer output, and including a first buffer configured to store current data CRC checksum values; and updated data CRC engine logic coupled to the CRC multiplexer output and the data multiplexer output, and including a second buffer configured to store updated data CRC checksum values, the updated data CRC engine logic operating in parallel with the current data CRC engine logic.

5 . The IC of claim 4 , wherein current data CRC checksum operations of the current data CRC engine logic, write request operations, and updated data CRC checksum operations of the updated data CRC engine logic are performed within a target update interval.

6 . The IC of claim 1 , wherein the IC is a power management IC (PMIC) and the control circuitry includes a first set of voltage converters for the first peripheral and a second set of voltage converters for the second peripheral, the first and second sets of voltage converters configured to adjust respective output voltages responsive to configuration bits provided by addressable bytes of the storage.

7 . The IC of claim 1 , wherein the IC is configured to:
provide configuration bits from addressable bytes of the storage to the control circuitry responsive to an control circuitry update trigger for the control circuitry, valid current CRC checksum results, and valid updated current CRC checksum results if any; and provide status bits from addressable bytes of the storage to the first peripheral responsive to a status request from the first peripheral, valid current data CRC checksum results, and valid updated current CRC checksum results if any; and provide status bits from addressable bytes of the storage to the second peripheral responsive to a status request from the second peripheral, valid current data CRC checksum results, and valid updated current CRC checksum results if any.

8 . The IC of claim 7 , wherein the control circuitry includes an adjustable sensor responsive to configuration bits from the storage.

9 . The IC of claim 7 , wherein the control circuitry includes an adjustable driver or actuator controller responsive to configuration bits from the storage.

10 . The IC of claim 1 , further comprising a state machine having state machine outputs coupled to the storage interface, the state machine configured to:
write status bits and configuration bits to the storage; and clear status bits and configuration bits from the storage.

11 . The IC of claim 1 , wherein the IC, the first peripheral and the second peripheral are components of an advanced driver assistance system (ADAS) domain controller.

12 . A system, comprising:
a first peripheral having a first set of inputs and a first communication terminal; a second peripheral having a second set of inputs and a second communication terminal; an integrated circuit (IC) having:
a first set of peripheral outputs coupled to the first set of inputs;
a first peripheral terminal coupled to the first communication terminal;
a second set of peripheral outputs coupled to the second set of inputs;
a second peripheral terminal coupled to the second communication terminal;
a storage having a storage interface and addressable bytes, the storage interface coupled to the first and second peripheral terminals;
control circuitry having control circuitry inputs and control circuitry outputs, the control circuitry inputs coupled to the storage interface and configured to receive configuration bits provided by the storage responsive to a control circuitry update trigger, and the control circuitry outputs coupled to the first and second sets of peripheral outputs; and
a cyclic-redundancy check (CRC) engine coupled to the storage interface, the CRC engine configured to:
perform current data CRC checksum operations;
track internal write requests to the storage, external write requests to the storage from the first peripheral, and external write requests to the storage from the second peripheral; and
perform updated data CRC checksum operations responsive to any tracked write requests.

13 . The system of claim 12 , wherein the CRC engine includes:
arbitration logic having arbitration logic inputs and an arbitration logic output, the arbitration logic inputs coupled to the first peripheral terminal, the second peripheral terminal, and an internal write request source,

Assignees

• Texas Instruments Inc

Inventors

• Brandon Kevin William
• Van Oevelen Jacco

Classifications

• G06F11/1004 Primary

  to protect a block of data words, e.g. CRC or checksum (G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00) · CPC title

• G06F11/3062

  where the monitored property is the power consumption (power management in a computing system G06F1/3203) · CPC title

• G11C7/1075 Primary

  for multiport memories each having random access ports and serial ports, e.g. video RAM · CPC title

• G06F11/1068

  in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence) · CPC title

• G06F11/3037

  where the computing system component is a memory, e.g. virtual memory, cache (accessing, addressing or allocating within memory systems or architectures G06F12/00; checking stores for correct operation G11C29/00) · CPC title