Storage system and method for using subcodes and convolutional-based LDPC interleaved coding schemes with read threshold calibration support

Patent metadata

Field	Value
Publication number	US-11481271-B2
Application number	US-202117202601-A
Country	US
Kind code	B2
Filing date	Mar 16, 2021
Priority date	Mar 16, 2021
Publication date	Oct 25, 2022
Grant date	Oct 25, 2022

Abstract

A storage system generates a low-density parity check (LDPC) code from a plurality of subcodes. The storage system stores each subcode in a different page of a word line in the memory. The subcode can be stored in one plane in the memory or across multiple planes. When the subcodes are stored across multiple planes, they can be stored in a checkboard pattern.

First claim

What is claimed is:

1. A storage system comprising:
a memory; and
a controller coupled to the memory and configured to:
store each subcode of a plurality of subcodes in a different page of a word line in the memory; and
generate a low-density parity check (LDPC) code from the plurality of subcodes stored in the different pages of the word line in the memory.

2. The storage system of claim 1 , wherein the plurality of subcodes are stored in a same plane in the memory.

3. The storage system of claim 1 , wherein the plurality of subcodes are stored in different planes in the memory.

4. The storage system of claim 3 , wherein the plurality of subcodes are stored in a checkerboard pattern in the different planes in the memory.

5. The storage system of claim 1 , wherein the controller is further configured to calibrate a read threshold for a page of the memory.

6. The storage system of claim 5 , wherein the calibration is done using a subcode stored on the page being calibrated, and wherein the calibration is done based on subcode bits that are stored on the page and a set of parity check equations that involve solely the subcode bits.

7. The storage system of claim 5 , wherein the calibration is done using a histogram.

8. The storage system of claim 1 , wherein the controller is further configured to store interleaved codewords and non-interleaved codewords in the memory.

9. The storage system of claim 8 , wherein the interleaved codewords and the non-interleaved codewords are stored in different word lines, different word line zones, or different blocks in the memory.

10. The storage system of claim 8 , wherein the non-interleaved codewords are used for read threshold calibration.

11. The storage system of claim 1 , wherein the memory comprises a three-dimensional memory.

12. In a storage system comprising a memory, a method comprising:
generating a convolutional low-density parity check (CLDPC) code; and
storing different portions of the CLDPC code in different pages of a word line in the memory; and
storing interleaved codewords and non-interleaved codewords in the memory, wherein the interleaved codewords and the non-interleaved codewords are stored in different word lines, different word line zones, or different blocks in the memory.

13. The method of claim 12 , wherein the different portions of the CLDPC code are stored in a same plane in the memory.

14. The method of claim 12 , wherein the different portions of the CLDPC code are stored in different planes in the memory.

15. The method of claim 14 , wherein the different portions of the CLDPC code are stored in a checkerboard pattern in the different planes in the memory.

16. The method of claim 12 , further comprising calibrating a read threshold for a page of the memory based on a portion of CLDPC code bits that are stored on a calibrated page and based on a set of parity check equations that involve solely the portion of CLDPC code bits.

17. The method of claim 12 , further comprising calibrating a read threshold for a page of the memory using a histogram.

18. The method of claim 12 , wherein the memory comprises a three-dimensional memory.

19. A storage system comprising:
a memory;
means for storing each subcode of a plurality of subcodes in a different page of a word line in the memory; and
means for generating a low-density parity check (LDPC) code from the plurality of subcodes stored in the different pages of the word line in the memory.

20. The storage system of claim 19 , wherein the LDPC code is generated during encoding.

21. The storage system of claim 1 , wherein the LDPC code is generated during encoding.

Assignees

• Western Digital Tech Inc

Inventors

• Sharon Eran
• Goldenberg Idan
• Alrod Idan
• Zamir Ran
• Bazarsky Alexander

Classifications

• G11C16/10

  Programming or data input circuits · CPC title

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title

• G06F2212/7207

  management of metadata or control data · CPC title

• G06F12/0238

  Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory · CPC title

• G06F11/1068 Primary

  in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence) · CPC title