Method and data storage device to estimate a number of errors using convolutional low-density parity-check coding

Patent metadata

Field	Value
Publication number	US-10063258-B2
Application number	US-201615265045-A
Country	US
Kind code	B2
Filing date	Sep 14, 2016
Priority date	Mar 4, 2016
Publication date	Aug 28, 2018
Grant date	Aug 28, 2018

Abstract

In an illustrative example, a method includes sensing at least a portion of a representation of a convolutional low-density parity-check (CLDPC) codeword stored at a memory of a data storage device. The method further includes receiving the portion of the representation of the CLDPC codeword at a controller of the data storage device. The method further includes performing one or more management operations associated with the memory based on an estimated number of errors of the portion of the representation of the CLDPC codeword.

First claim

What is claimed is:

1. A method of operation of a data storage device that includes a controller and a memory, the method comprising:
sensing at least a portion of a representation of a convolutional low-density parity-check (CLDPC) codeword stored at a storage region of a memory of a data storage device;
receiving the portion of the representation of the CLDPC codeword at a controller of the data storage device; and
based on an estimated number of errors of the portion of the representation of the CLDPC codeword, performing one or more management operations associated with the memory, wherein performing the one or more management operations includes adjusting one or more of a number of pulses of a programming signal used to write data to the storage region, adjusting a voltage level of the programming signal, or adjusting a duration of the programming signal, and
wherein use of the portion of the representation of the CLDPC codeword to initiate the one or more management operations reduces an amount of information transferred from the memory to the controller as compared to sending all of the representation of the CLDPC codeword from the memory to the controller.

2. The method of claim 1 , wherein performing the one or more management operations further includes performing one or more of a memory management operation associated with the storage region or a health management operation associated with the storage region.

3. The method of claim 2 , wherein the memory management operation is performed in response to detecting that the estimated number of errors satisfies a threshold.

4. The method of claim 2 , wherein performing the memory management operation includes one or more of performing a read scrub operation targeting the storage region or detecting a status of a write operation to write the CLDPC codeword to the storage region.

5. The method of claim 2 , wherein the health management operation includes adjusting a trim level associated with the storage region, initiating a wear leveling operation associated with the storage region, or adjusting an error correcting code (ECC) parameter associated with the storage region.

6. The method of claim 1 , further comprising determining the estimated number of errors prior to initiating a decode operation to decode the portion or without initiating the decode operation.

7. The method of claim 6 , wherein the decode operation is performed based on a parity check matrix having an upper right corner of zero values.

8. The method of claim 6 , wherein determining the estimated number of errors includes determining a bit error rate (BER) of the portion based on a number of unsatisfied checks associated with the portion.

9. The method of claim 1 , wherein the portion includes a first number of bits, and wherein the CLDPC codeword includes a second number of bits that is greater than the first number of bits.

10. The method of claim 1 , further comprising:
determining a second estimated number of errors associated with a second portion of the representation; and
determining a difference between the estimated number of errors and the second estimated number of errors.

11. The method of claim 10 , further comprising re-sensing the representation of the CLDPC codeword in response to determining that the difference satisfies a threshold.

12. A data storage device comprising:
a memory configured to store a convolutional low-density parity-check (CLDPC) codeword at a storage region of the memory; and
a controller coupled to the memory, the controller configured to access a portion of a representation of the CLDPC codeword and to initiate one or more management operations at the memory based on an estimated number of errors of the portion of the representation of the CLDPC codeword, the controller further configured adjust, in connection with the one or more management operations, one or more of a number of pulses of a programming signal used to write data to the storage region, a voltage level of the programming signal, or a duration of the programming signal,
wherein use of the portion of the representation of the CLDPC codeword to initiate the one or more management operations reduces an amount of information transferred from the memory to the controller as compared to sending all of the representation of the CLDPC codeword from the memory to the controller.

13. The data storage device of claim 12 , further comprising an error detection circuit configured to determine the estimated number of errors based on a number of unsatisfied checks associated with the portion.

14. The data storage device of claim 12 , wherein the controller includes a decoder, and wherein the controller is further configured to determine the estimated number of errors prior to inputting the portion to the decoder.

15. The data storage device of claim 14 , wherein the decoder is further configured to decode the CLDPC codeword based on a parity check matrix having an upper right set of values of zero.

16. A device comprising:
means for storing a convolutional low-density parity-check (CLDPC) codeword; and
means for receiving a portion of a representation of the CLDPC codeword from the means for storing, for initiating one or more management operations at the means for storing based on an estimated number of errors associated with the portion of the representation of the CLDPC codeword, and for adjusting, in connection with the one or more management operations, one or more of a number of pulses of a programming signal used to write data to a storage region of the means for storing, a voltage level of the programming signal, or a duration of the programming signal,
wherein use of the portion of the representation of the CLDPC codeword to initiate the one or more management operations reduces an amount of information transferred from the means for storing to the means for receiving as compared to sending all of the representation of the CLDPC codeword from the means for storing to the means for receiving.

17. The device of claim 16 , further comprising:
an error detection circuit configured to determine the estimated number of errors; and
a decoder coupled to the error detection circuit and configured to receive an indication of the estimated number of errors from the error detection circuit and to decode the representation of the CLDPC codeword based on the estimated number of errors.

18. The device of claim 17 , wherein the decoder is further configured to decode the representation based on a decoding window, and wherein the portion has a size corresponding to the decoding window.

19. The device of claim 16 , wherein the portion has a leftmost position within the CLDPC codeword.

20. The device of claim 16 , wherein the portion has a rightmost position within the CLDPC codeword.

21. The device of claim 16 , wherein the portion is selected from a leftmost position of the CLDPC codeword and from a rightmost position of the CLDPC codeword.

Assignees

• Sandisk Technologies Llc

Inventors

• Goldenberg Idan
• Ilani Ishai
• Bazarsky Alexander
• Rom Rami

Classifications

• H03M13/612

  Aspects specific to channel or signal-to-noise ratio estimation (H03M13/63 takes precedence) · CPC title

• H03M13/1108

  Hard decision decoding, e.g. bit flipping, modified or weighted bit flipping · CPC title

• G06F11/1052

  Bypassing or disabling error detection or correction · CPC title

• H03M13/3723

  using means or methods for the initialisation of the decoder · CPC title

• H03M13/6325

  Error control coding in combination with demodulation · CPC title