Semiconductor devices and methods of fabricating the same

Patent metadata

Field	Value
Publication number	US-11476327-B2
Application number	US-202117176667-A
Country	US
Kind code	B2
Filing date	Feb 16, 2021
Priority date	Jul 20, 2020
Publication date	Oct 18, 2022
Grant date	Oct 18, 2022

Abstract

A semiconductor device includes a gate electrode extending in a first direction, on a substrate, first outer spacers extending along side surfaces of the gate electrode, a first active pattern extending in a second direction, which intersects the first direction, to penetrate the gate electrode and the first outer spacers, epitaxial patterns on the first active pattern and on side surfaces of the first outer spacers, second outer spacers between the first outer spacers and the epitaxial patterns and inner spacers between the substrate and the first active pattern and between the gate electrode and the epitaxial patterns, wherein in a cross section that intersects the second direction, at least parts of the second outer spacers are on side surfaces of the first active pattern and side surfaces of the inner spacers.

First claim

What is claimed is:

1. A semiconductor device comprising:
a gate electrode extending in a first direction, on a substrate;
first outer spacers extending along side surfaces of the gate electrode;
a first active pattern extending in a second direction to penetrate the gate electrode and the first outer spacers, wherein the second direction intersects the first direction;
epitaxial patterns on the first active pattern and on side surfaces of the first outer spacers;
second outer spacers between the first outer spacers and the epitaxial patterns; and
inner spacers between the substrate and the first active pattern and between the gate electrode and the epitaxial patterns,
wherein, in a cross section that intersects the second direction, at least parts of the second outer spacers are on side surfaces of the first active pattern and side surfaces of the inner spacers, and
wherein top surfaces of the second outer spacers are lower than a top surface of the gate electrode.

2. The semiconductor device of claim 1 , wherein a dielectric constant of the second outer spacers is greater than a dielectric constant of the first outer spacers.

3. The semiconductor device of claim 1 , wherein a dielectric constant of the second outer spacers is greater than a dielectric constant of the inner spacers.

4. The semiconductor device of claim 1 , further comprising third outer spacers extending along side surfaces of the first outer spacers,
wherein the second outer spacers are on first portions of the first outer spacers, and
wherein the third outer spacers are on second portions of the first outer spacers.

5. The semiconductor device of claim 4 , wherein a dielectric constant of the second outer spacers is greater than a dielectric constant of the first outer spacers and a dielectric constant of the third outer spacers.

6. The semiconductor device of claim 1 , wherein the top surfaces of the second outer spacers are substantially coplanar with top surfaces of the epitaxial patterns.

7. The semiconductor device of claim 1 , wherein a thickness of the second outer spacers is smaller than a thickness of the inner spacers.

8. The semiconductor device of claim 1 , further comprising a second active pattern spaced apart from the first active pattern and extending in the second direction to penetrate the gate electrode and the first outer spacers,
wherein the inner spacers are between the first and second active patterns.

9. The semiconductor device of claim 1 , wherein the epitaxial patterns comprise n-type impurities.

10. A semiconductor device comprising:
a gate electrode extending in a first direction, on a substrate;
first outer spacers extending along side surfaces of the gate electrode;
an active pattern extending in a second direction to penetrate the gate electrode and the first outer spacers, wherein the second direction intersects the first direction;
epitaxial patterns on the active pattern and on side surfaces of the first outer spacers, the epitaxial patterns protruding away from the substrate beyond a top surface of the active pattern;
second outer spacers between the first outer spacers and the epitaxial patterns and on the top surface of the active pattern; and
third outer spacers extending along side surfaces of the first outer spacers, top surfaces of the second outer spacers, and top surfaces of the epitaxial patterns,
wherein a dielectric constant of the second outer spacers is greater than a dielectric constant of the first outer spacers and a dielectric constant of the third outer spacers, and
wherein the top surfaces of the second outer spacers are lower than a top surface of the gate electrode.

11. The semiconductor device of claim 10 , further comprising inner spacers between the substrate and the active pattern and between the gate electrode and the epitaxial patterns.

12. The semiconductor device of claim 11 , wherein the dielectric constant of the second outer spacers is greater than a dielectric constant of the inner spacers.

13. The semiconductor device of claim 10 , wherein the top surfaces of the second outer spacers are concave.

14. The semiconductor device of claim 10 , wherein a height of uppermost parts of the second outer spacers is smaller than a height of uppermost parts of the epitaxial patterns relative to the substrate.

15. The semiconductor device of claim 10 , wherein the epitaxial patterns comprise n-type impurities.

16. The semiconductor device of claim 10 , further comprising:
a gate dielectric film between the gate electrode and the first outer spacers and between the gate electrode and the active pattern.

17. A semiconductor device comprising:
a substrate including an n-type metal-oxide semiconductor (NMOS) region and a p-type metal-oxide semiconductor (PMOS) region;
a first gate electrode extending in a first direction on the NMOS region;
a first active pattern extending in a second direction to penetrate the first gate electrode, wherein the second direction intersects the first direction;
epitaxial patterns on the first active pattern and on side surfaces of the first gate electrode;
a second gate electrode extending in a third direction, on the PMOS region;
a second active pattern extending in a fourth direction to penetrate the second gate electrode, wherein the fourth direction intersects the third direction;
first outer spacers extending along side surfaces of the first gate electrode and side surfaces of the second gate electrode;
second outer spacers between the first outer spacers and the epitaxial patterns; and
third outer spacers extending along side surfaces of the first outer spacers, top surfaces of the second outer spacers, and top surfaces of the epitaxial patterns,
wherein a dielectric constant of the second outer spacers is greater than a dielectric constant of the first outer spacers and a dielectric constant of the third outer spacers, and
wherein the top surfaces of the second outer spacers are lower than a top surface of the first gate electrode.

18. The semiconductor device of claim 17 , further comprising inner spacers between the substrate and the first active pattern and between the first gate electrode and the epitaxial patterns,
wherein the dielectric constant of the second outer spacers is greater than a dielectric constant of the inner spacers.

19. The semiconductor device of claim 18 , wherein the dielectric constant of the first outer spacers, the dielectric constant of the third outer spacers, and the dielectric constant of the inner spacers are 5 or less.

20. The semiconductor device of claim 18 , wherein the first outer spacers, the third outer spacers, and the inner spacers comprise silicon oxynitride, silicon carbonitride, silicon carbide, silicon oxycarbide, silicon boron nitride, silicon boron carbonitride, and/or silicon oxycarbonitride, and
wherein the second outer spacers comprise silicon nitride.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Yeom Dong Hyuk
• Lee Kwan Heum
• Kim Jun Kyum
• Park Seong Hwa
• Seo So Hyun

Classifications

• B82Y10/00

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• H01L29/0847

  Electricity · mapped topic

• H01L21/823864

  Electricity · mapped topic

• H01L29/0653 Primary

  Electricity · mapped topic

• H01L29/1033

  Electricity · mapped topic