Gate spacer and inner spacer formation for nanosheet transistors having relatively small space between gates

Patent metadata

Field	Value
Publication number	US-10566445-B2
Application number	US-201815944322-A
Country	US
Kind code	B2
Filing date	Apr 3, 2018
Priority date	Apr 3, 2018
Publication date	Feb 18, 2020
Grant date	Feb 18, 2020

Abstract

Embodiments of the invention are directed to method of fabricating a semiconductor device. A non-limiting embodiment of the method includes performing fabrication operations to form a nanosheet field effect transistor (FET) device on a substrate, wherein the fabrication operations include forming gate spacers along a gate region of the nanosheet FET device, wherein each of the gate spacers comprises an upper segment and a lower segment.

First claim

What is claimed is:

1. A method of fabricating a semiconductor device, the method comprising:
performing fabrication operations to form a nanosheet field effect transistor (FET) device on a substrate, wherein the fabrication operations include:
forming gate spacers along a gate region of the nanosheet FET device;
wherein each of the gate spacers comprises an upper segment and a lower segment;

wherein forming the gate spacers comprises:
forming dummy gate spacers along the gate region of the nanosheet FET device;
using the dummy gates spacers as masks to remove portions of channel nanosheets of the nanosheet FET device; and
replacing the dummy gate spacers with the gate spacers;

wherein replacing the dummy gate spacers with the gate spacers comprises:
forming a layer of the first type of material along the gate region of the nanosheet FET device; and
replacing an upper region of the layer of the first type of material with a layer of the second type of material;
wherein the layer of the second type of material comprises the upper segment of the gate spacer; and

wherein replacing the dummy gate spacers with the gate spacers further comprises forming the lower segment of the gate spacer by using the upper segment of the gate spacer as a mask for removing portions of a lower region of the layer of the first type of material.

2. The method of claim 1 , wherein:
the upper segment comprises a second type of material; and
the lower segment comprises a first type of material.

3. The method of claim 1 , wherein the first type of material comprises a first type of low-k material.

4. The method of claim 3 , wherein the second type of material comprises a second type of low-k material.

5. The method of claim 2 , wherein the fabrication operations further comprise forming inner spacers between channel nano sheets of the nanosheet FET device.

6. The method of claim 5 , wherein inner spacers comprise the first type of material.

7. The method of claim 6 , wherein the first type of material comprises a first type of low-k material.

8. The method of claim 7 , wherein the second type of material comprises a second type of low-k material.

9. A method of fabricating a semiconductor device, the method comprising:
performing fabrication operations to form a nanosheet field effect transistor (FET) device on a substrate, wherein the fabrication operations include:
forming gate spacers along a gate region of the nanosheet FET device; and
forming inner spacers between channel nanosheets of the nanosheet FET device;
wherein each of the gate spacers comprises an upper segment and a lower segment;
wherein the upper segment comprises a second type of material;
wherein the lower segment comprises a first type of material;
wherein inner spacers comprise the first type of material;

wherein forming the gate spacers comprises:
forming dummy gate spacers along the gate region of the nanosheet FET device;
using the dummy gates spacers as masks to remove portions of channel nanosheets of the nanosheet FET device; and
replacing the dummy gate spacers with the gate spacers;

wherein replacing the dummy gate spacers with the gate spacers comprises:
forming a layer of the first type of material along the gate region of the nanosheet FET device; and
replacing an upper region of the layer of the first type of material with a layer of the second type of material;
wherein the layer of the second type of material comprises the upper segment of the gate spacer; and

wherein replacing the dummy gate spacers with the gate spacers further comprises forming the lower segment of the gate spacer by using the upper segment of the gate spacer as a mask for removing portions of a lower region of the layer of the first type of material.

10. The method of claim 9 , wherein:
the first type of material comprises a first type of low-k material; and
the second type of material comprises a second type of low-k material.

Assignees

• IBM

Inventors

• Bi Zhenxing
• Cheng Kangguo
• Loubet Nicolas J
• Miao Xin
• Xu Wenyu
• Zhang Chen

Classifications

• H01L29/6681

  Electricity · mapped topic

• H01L29/7853

  Electricity · mapped topic

• H01L29/0673

  Electricity · mapped topic

• H01L29/6656 Primary

  Electricity · mapped topic

• H01L29/6653

  Electricity · mapped topic