Method for dicing a semiconductor substrate into a plurality of dies

Patent metadata

Field	Value
Publication number	US-11476162-B2
Application number	US-202017038737-A
Country	US
Kind code	B2
Filing date	Sep 30, 2020
Priority date	Sep 30, 2019
Publication date	Oct 18, 2022
Grant date	Oct 18, 2022

Abstract

A method is provided for dicing a semiconductor substrate into a plurality of dies, the semiconductor substrate having a front side including a plurality of device areas, a back side, and a plurality of through substrate vias. The method includes defining, from the front side, at least one trench to be formed between adjacent device areas, forming the at least one trench, from the front side of the semiconductor substrate, arranging a protective layer on the front side of the semiconductor substrate, thinning the semiconductor substrate from the back side to reduce the thickness of the semiconductor substrate, processing the back side of the semiconductor substrate to form at least one contact, the contact contacting at least one through substrate via, etching through the minor portion of the thickness of the semiconductor substrate underneath the at least one trench, and dicing the semiconductor substrate into the plurality of dies.

First claim

What is claimed is:

1. A method for dicing a semiconductor substrate into a plurality of dies, wherein the semiconductor substrate comprises a front side provided with a plurality of device areas, a back side, and a plurality of through substrate vias, the method comprising:
defining, from the front side of the semiconductor substrate, at least one trench to be formed between adjacent device areas;
forming the at least one trench, from the front side of the semiconductor substrate, such that a major portion of a thickness of the semiconductor substrate is removed in the at least one trench, thereby leaving a minor portion of the thickness of the semiconductor substrate underneath the at least one trench;
arranging a protective layer on the front side of the semiconductor substrate, the protective layer covering at least a plurality of device areas;
thinning the semiconductor substrate from the back side to reduce the thickness of the semiconductor substrate such that at least a portion of the minor portion of the thickness of the semiconductor substrate remains underneath the at least one trench;
processing the back side of the semiconductor substrate to form at least one contact, the contact contacting at least one through substrate via;
etching, from the back side of the semiconductor substrate, through the minor portion of the thickness of the semiconductor substrate underneath the at least one trench, thereby separating the semiconductor substrate into a plurality of device areas arranged underneath the protective layer; and
dicing the semiconductor substrate into the plurality of dies.

2. The method according to claim 1 , wherein a width of the at least one trench is in a range of 0.5 to 50 μm.

3. The method according to claim 1 , wherein the minor portion of the thickness of the semiconductor substrate underneath the at least one trench has a thickness in a range of 0.3 to 100 μm.

4. The method according to claim 1 , wherein the at least one trench comprises two parallel trenches extending between the adjacent device areas.

5. The method according to claim 1 , wherein arranging the protective layer comprises:
depositing a bonding material on the front side of the semiconductor substrate; and
attaching a carrier wafer to the bonding material.

6. The method according to claim 5 , wherein dicing the semiconductor substrate into the plurality of dies comprises separating the bonding material of the protective layer from the front side of the semiconductor substrate.

7. The method according to claim 5 , wherein dicing the semiconductor substrate into the plurality of dies comprises separating the bonding material of the protective layer from the carrier wafer leaving the bonding material of the protective layer on the front side of the semiconductor substrate.

8. The method according to claim 5 , wherein the carrier wafer is a light transparent wafer.

9. The method according to claim 1 , wherein defining the at least one trench to be formed between adjacent device areas comprises:
forming a photoresist on the front side of the semiconductor substrate covering a plurality of device areas; and
patterning the photoresist thereby defining the at least one trench between the adjacent device areas.

10. The method according to claim 9 , wherein forming the at least one trench comprises etching the at least one trench, from the front side of the semiconductor substrate, using the photoresist as an etch mask.

11. The method according to claim 1 , wherein thinning the semiconductor substrate further comprises revealing at least one through substrate via.

12. The method according to claim 1 , wherein the method further comprises:
prior to the step of processing the back side of the semiconductor substrate, forming, from the back side of the semiconductor substrate, an opening underneath at least one through substrate via to reveal the at least one through substrate via.

13. The method according to claim 1 , wherein processing the back side of the semiconductor substrate to form the at least one contact further comprises:
forming a passivation layer on the back side of the semiconductor substrate;
patterning the passivation layer underneath the at least one through substrate via to form an opening exposing at least a portion of the at least one through substrate via; and
forming a contact contacting the exposed portion of the at least one through substrate via.

14. The method according to claim 1 , wherein the semiconductor substrate comprises Si.

15. A semiconductor substrate prepared by a method for dicing the semiconductor substrate into a plurality of dies, wherein the semiconductor substrate comprises a front side provided with a plurality of device areas, a back side, and a plurality of through substrate vias, the method comprising the steps of:
defining, from the front side of the semiconductor substrate, at least one trench to be formed between adjacent device areas on the front side of the semiconductor substrate;
forming the at least one trench, from the front side of the semiconductor substrate, such that a major portion of a thickness of the semiconductor substrate is removed in the at least one trench, thereby leaving a minor portion of the thickness of the semiconductor substrate underneath the at least one trench;
arranging a protective layer on the front side of the semiconductor substrate, the protective layer covering at least a plurality of device areas;
thinning the semiconductor substrate from the back side of the semiconductor substrate to reduce the thickness of the semiconductor substrate such that at least a portion of the minor portion of the thickness of the semiconductor substrate remains underneath the at least one trench;
processing the back side of the semiconductor substrate to form at least one contact, the contact contacting at least one through substrate via;
etching, from the back side of the semiconductor substrate, through the minor portion of the thickness of the semiconductor substrate underneath the at least one trench, thereby separating the semiconductor substrate into a plurality of device areas arranged underneath the protective layer; and
dicing the semiconductor substrate into the plurality of dies.

16. The semiconductor substrate according to claim 15 , wherein a width of the at least one trench is in a range of 0.5 to 50 μm.

17. The semiconductor substrate according to claim 15 , wherein the minor portion of the thickness of the semiconductor substrate underneath the at least one trench has a thickness in a range of 0.3 to 100 μm.

18. The semiconductor substrate according to claim 15 , wherein the at least one trench comprises two parallel trenches extending between the adjacent device areas.

19. The semiconductor substrate according to claim 15 , wherein thinning the semiconductor substrate further comprises revealing at least one through substrate via.

20. A semiconductor die prepared by a method for dicing a semiconductor substrate into a plurality of dies, wherein the semiconductor substrate comprises a front side provided with a plurality of device areas, a back side, and a plurality of through substrate vias, the method comprising the steps of:
defining, from the front side of the semiconductor substrate, at least one trench to be formed between adjacent device areas on the front side of the semiconductor substrate;
forming the at least one trench, from the front side of the semiconductor substrate, such that a major portion of a thickness of the sem

Assignees

• Imec Vzw

Inventors

• Holsteyns Frank
• Beyne Eric
• Lorant Christophe
• Braun Simon

Classifications

• H10W74/147

  the encapsulations being multilayered · CPC title

• H10W74/017

  Auxiliary layers for moulds, e.g. release layers or layers preventing residue · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title