Nonvolatile memory device and method of operating a nonvolatile memory

Patent metadata

Field	Value
Publication number	US-11475956-B2
Application number	US-202117234175-A
Country	US
Kind code	B2
Filing date	Apr 19, 2021
Priority date	Nov 2, 2020
Publication date	Oct 18, 2022
Grant date	Oct 18, 2022

Abstract

A method of operating a nonvolatile memory device which includes at least one memory block is provided. The method includes providing a plurality of word-lines with a voltage during a word-line set-up period, precharging a plurality of driving lines with a voltage during a word-line development period, detecting a voltage drop of a sensing node during a sensing period, and detecting leakage based on the voltage drop.

First claim

What is claimed is:

1. A method of operating a nonvolatile memory device which comprises at least one memory block comprising a plurality of cell strings, each of which comprises a string selection transistor, a plurality of memory cells and a ground selection transistor which are connected in series and arranged in a vertical direction between a bit-line and a source line, the method comprising:
during a word-line set-up period and while applying a first voltage to a block word-line that is coupled to each gate of a plurality of pass transistors which respectively connect a string selection line, a plurality of word-lines and a ground selection line to a plurality of driving lines, applying a second voltage to the plurality of driving lines, commonly coupled to a sensing node, to provide the plurality of word-lines with a third voltage, the string selection line being coupled to the string selection transistor, the plurality of word-lines being coupled to the plurality of memory cells and the ground selection line being coupled to the ground selection transistor;
during a word-line development period and while precharging the plurality of driving lines with the second voltage, applying a fourth voltage to the block word-line to turn-off the plurality of pass transistors to develop target word-lines from among the plurality of word-lines; and
during a sensing period, applying a fifth voltage smaller than the first voltage to the block word-line, detecting a voltage drop of the sensing node, and detecting leakage of the target word-lines based on the voltage drop.

2. The method of claim 1 , wherein:
the sensing period precedes a program operation of a program loop on the at least one memory block, and
the method further comprises ending the program loop based on it being determined that the leakage occurs in at least one of the plurality of word-lines.

3. The method of claim 1 , wherein during the word-line set-up period,
a level of the second voltage is greater than a level of the first voltage, and
a level of the third voltage is smaller than the level of the first voltage by a first threshold voltage.

4. The method of claim 3 , wherein during the sensing period,
a level of the fifth voltage is greater than a level of each of the target word-lines by the first threshold voltage, and
the method further comprises determining the leakage has occurred in a word-line coupled to at least one pass transistor that is turned-on by the fifth voltage from among the plurality of pass transistors.

5. The method of claim 1 , wherein during the word-line set-up period,
a level of the first voltage is greater than a level of the second voltage, and
a level of the third voltage is substantially equal to the level of the first voltage.

6. The method of claim 5 , wherein during the sensing period,
a level of the fifth voltage is greater than a level of each of the target word-lines by a first threshold voltage, and
the method further comprises determining that the leakage has occurred in a word-line coupled to at least one pass transistor that is turned-on by the fifth voltage from among the plurality of pass transistors.

7. The method of claim 1 , wherein the plurality of driving lines are coupled to the sensing node by a plurality of selection switches.

8. The method of claim 7 , wherein the target word-lines correspond to each of the plurality of word-lines selected by enabling the plurality of selection switches.

9. The method of claim 7 , wherein the target word-lines correspond to either even word-lines or odd word-lines selected from among the plurality of word-lines by enabling a portion of the plurality of selection switches.

10. The method of claim 1 , further comprising performing an erase operation on the at least one memory block,
wherein the detecting the leakage of the target word-lines is performed after the erase operation.

11. A nonvolatile memory device comprising:
at least one memory block comprising a plurality of cell strings where each of the plurality of cell strings, each of which comprises a string selection transistor, a plurality of memory cells and a ground selection transistor which are connected in series and arranged in a vertical direction between a bit-line and a source line; and
a control circuit configured to control a leakage detection operation by:
during a word-line set-up period and while applying a first voltage to a block word-line that is coupled to each gate of a plurality of pass transistors which respectively connect a string selection line, a plurality of word-lines and a ground selection line to a plurality of driving lines, applying a second voltage to the plurality of driving lines, commonly coupled to a sensing node, to provide the plurality of word-lines with a third voltage, the string selection line being coupled to the string selection transistor, the plurality of word-lines being coupled to the plurality of memory cells and the ground selection line being coupled to the ground selection transistor;
during a word-line development period and while precharging the plurality of driving lines with the second voltage, applying a fourth voltage to the block word-line to turn-off the plurality of pass transistors to develop target word-lines from among the plurality of word-lines; and
during a sensing period, applying a fifth voltage smaller than the first voltage to the block word-line, detecting a voltage drop of the sensing node, and detecting leakage of the target word-lines based on the voltage drop.

12. The nonvolatile memory device of claim 11 , wherein:
the control circuit is configured to perform the leakage detection operation during a program operation of a program loop on the at least one memory block; and
the control circuit is configured to end the program loop on the at least one memory block based on the leakage occurring in at least one of the plurality of word-lines.

13. The nonvolatile memory device of claim 11 , further comprising:
a voltage generator configured to generate word-line voltages based on a control signal;
an address decoder configured to provide the word-line voltages to the at least one memory block; and
a leakage detector coupled to the sensing node,
wherein the address decoder comprises:
a pass switch circuit comprising a plurality of pass switch transistors;
a first voltage transfer circuit;
a second voltage transfer circuit connected to the voltage generator and the first voltage transfer circuit at the sensing node; and
a selection switch circuit connected between the first voltage transfer circuit and the plurality of driving lines, the selection switch circuit comprising a plurality of selection transistors configured to connect the first voltage transfer circuit to the plurality of driving lines.

14. The nonvolatile memory device of claim 13 , wherein the control circuit is configured to control the voltage generator and the address decoder such that:
a level of the second voltage is greater than a level of the first voltage, and a level of the third voltage is smaller than the level of the first voltage by a first threshold voltage during the word-line set-up period; and
a level of the fifth voltage is greater than a level of each of the target word-lines by the first threshold voltage during the sensing period, and
wherein the leakage detector is configured to determine that leakage occurs based on a voltage level of the sensing node dropping during the sensing period.

15. The nonvolatile memory device of claim 13 , wherein the control circuit is configured to control the voltage generator and the

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Chaehoon
• Ko Junyoung
• Nam Sangwan
• Seo Minjae
• Seo Jiwon
• Lee Hojun

Classifications

• G11C16/0425

  comprising cells containing a merged floating gate and select transistor · CPC title

• G11C16/30

  Power supply circuits · CPC title

• G11C16/3459

  Circuits or methods to verify correct programming of nonvolatile memory cells · CPC title

• G11C16/3404

  Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells · CPC title

• G11C2029/1202

  Word line control · CPC title