Leakage current compensation device and semiconductor memory device

Patent metadata

Field	Value
Publication number	US-2020105345-A1
Application number	US-201916384381-A
Country	US
Kind code	A1
Filing date	Apr 15, 2019
Priority date	Oct 2, 2018
Publication date	Apr 2, 2020
Grant date	—

Abstract

A leakage current compensation device includes a current supply unit configured to supply a current to at least one operating cell, among a plurality of cells of a memory device disposed at intersections of wordlines and bitlines, a leakage current sensing unit configured to sense an amount of leakage current flowing to a non-operating cell among the cells to output a result value based on the sensed amount of leakage current, and a compensation current supply unit configured to receive the result value and supply a compensation current to the operating cell.

First claim

What is claimed is:

1 . A leakage current compensation device comprising:
a current supply unit configured to supply a current to at least one operating cell, among a plurality of cells of a memory device disposed at intersections of wordlines and bitlines; a leakage current sensing unit configured to sense an amount of leakage current flowing to a non-operating cell among the cells to output a result value based on the sensed amount of leakage current; and a compensation current supply unit configured to receive the result value and supply a compensation current to the operating cell.

2 . The leakage current compensation device of claim 1 , wherein the leakage current sensing unit includes a first sense amplifier configured to sense a voltage value at one end of the current supply unit.

3 . The leakage current compensation device of claim 2 , wherein the voltage value at the one end of the current supply unit is supplied to a first input terminal of the first sense amplifier, a first reference voltage is supplied to a second input terminal of the first sense amplifier, and the first sense amplifier compares the voltage value at the one end of the current supply unit with the first reference voltage to output the result value.

4 . The leakage current compensation device of claim 1 , wherein the leakage current sensing unit includes first to n-th sense amplifiers configured to sense the voltage value at the one end of the current supply unit, where n is an integer greater than or equal to 2.

5 . The leakage current compensation device of claim 4 , wherein the voltage value at the one end of the current supply unit is supplied to a first input terminal of each of the first to n-th sense amplifiers, and
first to nth reference voltages, different from each other, are supplied to a second input terminal of each of the first to n-th sense amplifiers.

6 . The leakage current compensation device of claim 5 , wherein the leakage current sensing unit compares the voltage value at the one end of the current supply unit with the respective first to n-th reference voltages to output different result values.

7 . The leakage current compensation device of claim 1 , further comprising:
a storage unit configured to store different compensation current information depending on at least one of different temperature intervals and different cell locations.

8 . The leakage current compensation device of claim 7 , further comprising:
a temperature sensing unit configured to sense a temperature of the plurality of cells or a surrounding temperature of the plurality of cells to generate sensed temperature information, wherein the temperature sensing unit transmits the sensed temperature information to the storage unit.

9 . The leakage current compensation device of claim 7 , wherein the compensation current supply unit receives the compensation current information and supplies a compensation current to the operating cell according to the received compensation current information.

10 . The leakage current compensation device of claim 1 , wherein the leakage current sensing unit comprises:
a regulator unit configured to sense the amount of leakage current flowing to the unselected bitlines which do not include a selected cell; and a current mirror unit configured to output the amount of the leakage current to the compensation current supply unit as the result value.

11 . The leakage current compensation device of claim 10 , wherein the regulator unit comprises:
an amplifier configured to provide an unselected voltage to the unselected bitlines; and a first transistor to which a current corresponding to a total value of leakage currents flowing to the unselected bitlines flows.

12 . A leakage current compensation device comprising:
a current supply unit configured to supply a current to at least one operating cell, among a plurality of cells of a memory device disposed at intersections of wordlines and bitlines; and a leakage current compensation unit configured to sense an amount of leakage current flowing to a non-operating cell among the cells during a sampling period before an operating period to determine a result value based on the sensed amount of leakage current and to supply a compensation current to the operating cell based on the result value during the operating period.

13 . The leakage current compensation device of claim 12 , further comprising:
a sampling voltage supply unit configured to supply a different sampling voltage based on a cell location, to one end of the current supply unit.

14 . The leakage current compensation device of claim 12 , further comprising:
a sampling voltage supply unit configured to supply a different sampling voltage based on a cell location and different temperature intervals, to one end of the current supply unit.

15 . The leakage current compensation device of claim 14 , further comprising:
a temperature sensing unit configured to sense a temperature of the plurality of cells or a surrounding temperature of the plurality of cells to generate sensed temperature information, wherein the temperature sensing unit transmits the sensed temperature information to the sampling voltage supply unit.

16 . The leakage current compensation device of claim 12 , wherein the leakage current compensation unit comprises:
a first transistor through which the compensation current passes; a switch configured to connect a drain terminal of the first transistor and a gate terminal of the first transistor to each other; and a capacitor configured to connect the gate terminal of the first transistor and a source terminal of the first transistor to each other.

17 . The leakage current compensation device of claim 16 , wherein the switch is a second transistor configured to receive a sampling period information signal through a gate terminal of the second transistor, and
a drain terminal of the second transistor and a source terminal of the second transistor are connected to the drain terminal of the first transistor and the gate terminal of the first transistor, respectively.

18 . The leakage current compensation device of claim 17 , wherein the sampling period information signal is a digital signal which is 1 during the sampling period and 0 outside the sampling period.

19 . The leakage current compensation device of claim 16 , wherein the capacitor stores the result value based on the amount of leakage current sensed during the sampling period, as a voltage value.

20 . A semiconductor memory device comprising:
a plurality of memory cells disposed at intersections of a plurality of wordlines and a plurality of bitlines; a current supply unit connected to one end of at least one wordline among the plurality of wordlines to supply a current to at least one operating cell among the plurality of memory cells; and a leakage current compensation unit configured to sense an amount of leakage current flowing to a non-operating cell of the memory cells to supply a compensation current to the operating cell according to the sensed amount of leakage current.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Baek Jong Min
• Kalluru Vivek Venkata
• Kim Jong Ryul
• Janjua Bilal Ahmad

Classifications

• G11C2013/0045

  Read using current through the cell · CPC title

• G11C2013/0078

  Write using current through the cell · CPC title

• G11C13/0033 Primary

  Disturbance prevention or evaluation; Refreshing of disturbed memory data · CPC title

• G11C13/0069

  Writing or programming circuits or methods · CPC title

• G11C7/04

  with means for avoiding disturbances due to temperature effects · CPC title