Method for an internal command of a first processing core with memory sub-system that caching identifiers for access commands

Patent metadata

Field	Value
Publication number	US-11474885-B2
Application number	US-202016841935-A
Country	US
Kind code	B2
Filing date	Apr 7, 2020
Priority date	Apr 7, 2020
Publication date	Oct 18, 2022
Grant date	Oct 18, 2022

Abstract

Methods, systems, and devices for caching identifiers for access commands are described. A memory sub-system can receive an access command to perform an access operation on a transfer unit of the memory sub-system. The memory sub-system can store an identifier associated with the access command in a memory component and can generate an internal command using a first core of the memory sub-system. In some embodiments, the memory sub-system can store the identifier in a shared memory that is accessible by the first core and can issue the internal command to perform the access operation on the memory sub-system.

First claim

What is claimed is:

1. A method, comprising:
receiving an access command to perform an access operation on a transfer unit of a memory sub-system;
storing an identifier associated with the access command in a memory component for storing identifiers associated with access commands;
generating, by a first core of the memory sub-system, an internal command configured for use by a plurality of hardware components of the memory sub-system and associated with the identifier;
storing the identifier associated with the internal command in a shared memory that is accessible by a plurality of first cores; and
issuing, by the first core, the internal command to perform the access operation on the memory sub-system.

2. The method of claim 1 , further comprising:
receiving, at one of the plurality of first cores, the identifier based at least in part on performing the access operation on the memory sub-system; and
determining whether the access operation was completed based at least in part on receiving the identifier.

3. The method of claim 2 , further comprising:
reading, to the shared memory, a command entry comprising the identifier from a queue comprising a plurality of command identifiers for performing access operations on the memory sub-system based at least in part on determining that the access operation was not completed; and
updating the internal command based at least in part on reading the command entry to the shared memory.

4. The method of claim 3 , further comprising:
allocating the identifier to the access command based at least in part on receiving the access command;
determining that an entry of the shared memory comprises the identifier; and
reading the entry comprising the identifier based at least in part on determining that the command entry comprises the identifier, wherein generating the internal command is based at least in part on reading the command entry.

5. The method of claim 1 , further comprising:
determining, by a coherency checker, whether the identifier matches one or more other identifiers stored in the shared memory based at least in part on issuing the internal command.

6. The method of claim 5 , further comprising:
updating the identifier associated with the access command based at least in part on the identifier matching one or more other identifiers stored in the shared memory, wherein the access operation associated with the identifier is updated to include the access operation associated with the identifier stored in the shared memory.

7. The method of claim 1 , wherein the internal command comprises:
information for performing the access operation on the memory sub-system.

8. The method of claim 1 , wherein the memory sub-system comprises a plurality of second cores that are different than the plurality of first cores, wherein the plurality of second cores are configured to access a memory device for storing data associated with a host system.

9. A system, comprising:
a plurality of memory components; and
a processing device, operatively coupled with the plurality of memory components, to:
receive an access command to perform an access operation on a transfer unit of a memory sub-system;
store an identifier associated with the access command in a memory component for storing identifiers associated with access commands;
generate, by a first core of the memory sub-system, an internal command configured for use by a plurality of hardware components of the memory sub-system and associated with the identifier;
store the identifier associated with the internal command in a shared memory that is accessible by a plurality of first cores; and
issue, by the first core, the internal command to perform the access operation on the memory sub-system.

10. The system of claim 9 , further comprising:
the processing device further to:
receive, at one of the plurality of first cores, the identifier based at least in part on performing the access operation on the memory sub-system; and
determine whether the access operation was completed based at least in part on receiving the identifier.

11. The system of claim 10 , further comprising:
the processing device further to:
read, to the shared memory, a command entry comprising the identifier from a queue comprising a plurality of command identifiers for performing access operations on the memory sub-system based at least in part on determining that the access operation was not completed; and
update the internal command based at least in part on reading the command entry to the shared memory.

12. The system of claim 11 , further comprising:
the processing device further to:
allocate the identifier to the access command based at least in part on receiving the access command;
determine that an entry of the shared memory comprises the identifier; and
read the entry comprising the identifier based at least in part on determining that the command entry comprises the identifier, wherein generating the internal command is based at least in part on reading the command entry.

13. The system of claim 9 , further comprising:
the processing device further to:
determine, by a coherency checker, whether the identifier matches one or more other identifiers stored in the shared memory based at least in part on issuing the internal command.

14. The system of claim 13 , further comprising:
the processing device further to:
update the identifier associated with the access command based at least in part on the identifier matching one or more other identifiers stored in the shared memory, wherein the access operation associated with the identifier is updated to include the access operation associated with the identifier stored in the shared memory.

15. The system of claim 9 , wherein the internal command comprises:
information for performing the access operation on the memory sub-system.

16. The system of claim 9 , wherein the memory sub-system comprises a plurality of second cores that are different than the plurality of first cores, wherein the plurality of second cores are configured to access a memory device for storing data associated with a host system.

17. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to:
receive an access command to perform an access operation on a transfer unit of a memory sub-system;
store an identifier associated with the access command in a memory component for storing identifiers associated with access commands;
generate, by a first core of the memory sub-system, an internal command configured for use by a plurality of hardware components of the memory sub-system and associated with the identifier;
store the identifier associated with the internal command in a shared memory that is accessible by a plurality of first cores; and
issue, by the first core, the internal command to perform the access operation on the memory sub-system.

18. The non-transitory computer-readable storage medium of claim 17 , the instructions, when executed by the processing device, cause the processing device to:
receive, at one of the plurality of first cores, the identifier based at least in part on performing the access operation on the memory sub-system; and
determine whether the access operation was completed based at least in part on receiving the identifier.

19. The non-transitory computer-readable storage medium of claim 18 , the instructions, when executed by the processing device, cause the processing device

Assignees

• Micron Technology Inc

Inventors

• Traver John
• Shoen Jay R

Classifications

• G06F2212/466

  Metadata, control data · CPC title

• G06F2212/214

  Solid state disk · CPC title

• G06F3/061

  Improving I/O performance · CPC title

• G06F3/0659 Primary

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F9/3836

  Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution · CPC title