Polishing pad, polishing apparatus and a method for polishing silicon wafer

US11471997B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11471997-B2
Application numberUS-202017136544-A
CountryUS
Kind codeB2
Filing dateDec 29, 2020
Priority dateJul 8, 2020
Publication dateOct 18, 2022
Grant dateOct 18, 2022

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

The present invention provides a polishing pad, a polishing apparatus and a polishing method for a silicon wafer. The polishing pad comprises a polishing surface in contact with the silicon wafer. The polishing surface is provided with at least one groove. When polishing the silicon wafer, the edge of the silicon wafer is at least partially suspended above the groove. The polishing pad, polishing apparatus and silicon wafer polishing method according to the present invention can reduce the polishing rate at the edge of the silicon wafer while keeping the polishing rate of the entire wafer basically unchanged, thereby improving the flatness of the edge thickness of the silicon wafer as well as improving the production yield.

First claim

Opening claim text (preview).

What is claimed is: 1. A polishing pad for polishing a silicon wafer comprising a polishing surface for contacting the silicon wafer, wherein the polishing pad has a first annular groove near a pad edge and a second annular groove near a pad center, and at least one drainage groove; wherein at least a partial edge of the silicon wafer suspends above at least one of the first annular groove, the second annular groove and the drainage groove during polishing; wherein the first annular groove has a width of 3 mm˜8 mm, a depth of 0.5 mm˜2 mm, an outer edge radius of 335 mm˜340 mm, and an inner edge radius of 330 mm˜335 mm; and the second annular groove has a width of 3 mm˜8 mm, a depth of 0.5 mm˜2 mm, an outer edge radius of 35 mm˜45 mm, and an inner edge radius of 30 mm˜40 mm; and wherein the drainage groove is arch and tangent with the outer edge of the second annular groove, and the drainage groove connects the second annular groove at one terminal, passes through the first annular groove, and connects to the edge of the polishing pad at another terminal. 2. The polishing pad of claim 1 , wherein a first distance is between the inner edge of the first annular groove and the outer edge of the second annular groove, and the first distance is less than a diameter of the silicon wafer; and second distance is between the outer edge of the first annular groove and the inner edge of the second annular groove, and the second distance is larger than the diameter of the silicon wafer. 3. The polishing pad of claim 1 , wherein the polishing pad, the first annular groove and the second annular groove are concentric. 4. A polishing apparatus for polishing a silicon wafer comprising: a polishing pad of claim 1 ; a driving device for driving the polishing pad disposed thereon to rotate; and a polishing head for fixing the silicon wafer to contact the front side of the silicon wafer with the polishing pad and suspend the edge of the silicon wafer above the first annular groove and/or the second annular groove of the polishing pad.

Assignees

Inventors

Classifications

  • of semiconductor materials · CPC title

  • by polishing · CPC title

  • B24B37/26Primary

    characterised by the shape of the lapping pad surface, e.g. grooved · CPC title

  • Control means for lapping machines or devices · CPC title

  • acting by the front face · CPC title

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Frequently asked questions

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What does patent US11471997B2 cover?
The present invention provides a polishing pad, a polishing apparatus and a polishing method for a silicon wafer. The polishing pad comprises a polishing surface in contact with the silicon wafer. The polishing surface is provided with at least one groove. When polishing the silicon wafer, the edge of the silicon wafer is at least partially suspended above the groove. The polishing pad, polishi…
Who is the assignee on this patent?
Zing Semiconductor Corp
What technology area does this patent fall under?
Primary CPC classification B24B37/26. Mapped technology areas include Operations & Transport.
When was this patent published?
Publication date Tue Oct 18 2022 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).