Three-dimensional memory devices and fabricating methods thereof

Patent metadata

Field	Value
Publication number	US-11469248-B2
Application number	US-202017112496-A
Country	US
Kind code	B2
Filing date	Dec 4, 2020
Priority date	Nov 16, 2017
Publication date	Oct 11, 2022
Grant date	Oct 11, 2022

Abstract

A three-dimensional (3D) NAND memory device is provided. The device comprises an alternating stack including a plurality of dielectric/conductive layer pairs each comprising a dielectric layer and a conductive layer. The device further comprises a conductive wall vertically penetrating through the alternating stack and extending in a horizontal direction, and a spacer layer on sidewalls of the conductive wall configured to insulate the conductive wall from the conductive layers of the alternating stack. The spacer layer comprises a first spacer sublayer having a first dielectric material, a second spacer sublayer having a second dielectric material, and a third spacer sublayer having a third dielectric material. The second spacer is sandwiched between the first spacer sublayer and the third spacer sublayer. A second k-value of the second dielectric material is higher than a first k-value of the first dielectric material and higher than a third k-value of the third dielectric material.

First claim

What is claimed is:

1. A three-dimensional (3D) NAND memory device, comprising:
an alternating dielectric/conductive stack including a plurality of dielectric/conductive layer pairs on a substrate, each of the plurality of dielectric/conductive layer pairs comprising a dielectric layer and a conductive layer;
a conductive wall vertically penetrating through the alternating dielectric/conductive stack and extending in a horizontal direction; and
a spacer layer on sidewalls of the conductive wall configured to insulate the conductive wall from the plurality of conductive layers of the alternating dielectric/conductive stack, comprising:
a first spacer sublayer having a first dielectric material;
a second spacer sublayer having a second dielectric material;
a third spacer sublayer having a third dielectric material; and
an isolation film having a composite structure including oxide, metal and nitride;
wherein the second spacer sublayer is sandwiched between the first spacer sublayer and the third spacer sublayer, and a second k-value of the second dielectric material is higher than a first k-value of the first dielectric material and higher than a third k-value of the third dielectric material.

2. The device of claim 1 , wherein:
each of the dielectric layers is silicon oxide having a thickness in a range from about 10 nm to about 150 nm;
each of the conductive layers is tungsten having a thickness in a range from about 10 nm to about 150 nm; and
the conductive wall includes tungsten.

3. The device of claim 1 , further comprising:
a doped region in the substrate below and in contact with the conductive wall.

4. The device of claim 1 , further comprising:
a plurality of channel structures; each penetrating vertically through the alternating dielectric/conductive stack;
wherein the conductive wall extends horizontally between the plurality of channel structures.

5. The device of claim 4 , wherein each of the plurality of channel structures comprises:
a channel hole extending vertically through the alternating dielectric/conductive stack;
a functional layer on a sidewall of the channel hole; and
a channel layer covering a sidewall of the functional layer.

6. The device of claim 5 , further comprising:
an insulating layer between the each dielectric layer and each conductive layer, and between the conductive layers and the functional layer.

7. The device of claim 1 , wherein:
the first dielectric material is a low temperature oxide material,
the second dielectric material is a nitride material; and
the third dielectric material is a low temperature oxide material or a high temperature oxide material.

8. The device of claim 1 , wherein:
the first spacer sublayer and the second spacer sublayer both have a plurality of recesses, each recess corresponding to one of the plurality of conductive layers.

9. The device of claim 1 , wherein:
the isolation film includes silicon oxide, titanium and titanium nitride, and is disposed between the third spacer sublayer and the conductive wall.

10. A three-dimensional (3D) NAND memory device, comprising:
an alternating dielectric/conductive stack including a plurality of dielectric/conductive layer pairs on a substrate, each of the plurality of dielectric/conductive layer pairs comprising a dielectric layer and a conductive layer;
a conductive wall vertically penetrating through the alternating dielectric/conductive stack and extending in a horizontal direction; and
a spacer layer on sidewalls of the conductive wall configured to insulate the conductive wall from the plurality of conductive layers of the alternating dielectric/conductive stack, wherein the spacer layer has a laminated structure, a surface of the laminated structure proximate to the conductive wall comprises an isolation film that has a composite structure including oxide, metal and nitride.

11. The device of claim 10 , wherein:
each of the dielectric layers is silicon oxide having a thickness in a range from about 10 nm to about 150 nm;
each of the conductive layers is tungsten having a thickness in a range from about 10 nm to about 150 nm; and
the conductive wall includes tungsten.

12. The device of claim 10 , further comprising:
a doped region in the substrate below and in contact with the conductive wall.

13. The device of claim 10 , further comprising:
a plurality of channel structures, each penetrating vertically through the alternating dielectric/conductive stack;
wherein the conductive wall extends horizontally between the plurality of channel structures.

14. The device of claim 13 , wherein each of the plurality of channel structures comprises:
a channel hole extending vertically through the alternating dielectric/conductive stack;
a functional layer on a sidewall of the channel hole; and
a channel layer covering a sidewall of the functional layer.

15. The device of claim 14 , further comprising:
an insulating layer between the each dielectric layer and each conductive layer, and between the conductive layers and the functional layer.

16. The device of claim 11 , wherein the spacer layer having the laminated structure comprises:
a first spacer sublayer having a first dielectric material;
a second spacer sublayer having a second dielectric material; and
a third spacer sublayer having a third dielectric material;
wherein the second spacer sublayer is sandwiched between the first spacer sublayer and the third spacer sublayer, and a second k-value of the second dielectric material is higher than a first k-value of the first dielectric material and higher than a third k-value of the third dielectric material.

17. The device of claim 16 , wherein:
the first dielectric material is a low temperature oxide material;
the second dielectric material is a nitride material; and
the third dielectric material is a low temperature oxide material or a high temperature oxide material.

18. The device of claim 16 , wherein:
the first spacer sublayer and the second spacer sublayer both have a plurality of recesses, each recess corresponding to one of the plurality of conductive layers.

19. The device of claim 16 , wherein:
the isolation film includes silicon oxide, titanium and titanium nitride, and is disposed between the third spacer sublayer and the conductive wall.

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Ding Lei
• Gao Jing
• Yang Chuan
• Yu lan fang
• Yan Ping
• Zhang Sen
• Xu Bo

Classifications

• H01L27/11556

  Electricity · mapped topic

• H01L27/11524

  Electricity · mapped topic

• H01L27/11582 Primary

  Electricity · mapped topic

• H01L27/1157

  Electricity · mapped topic

• H10B43/35

  with cell select transistors, e.g. NAND · CPC title